ΔΣ Modulator Overflow Frequency Detection for Oscillation Reset Control
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Solution Overview
Problem
Conventional semiconductor devices with ΔΣ modulators face issues with excessive resetting due to temporary overflows caused by noise, leading to inefficient restoration from oscillation states.
Innovation Solution
A semiconductor device comprising a ΔΣ modulator with a quantizer, overflow detection circuit, overflow frequency calculation circuit, oscillation judgment circuit, and oscillation halt circuit, which calculates and judges the overflow frequency to determine if the modulator is in an oscillation state, and only resets when the oscillation is continuous.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the microcomputer resets the ΔΣ modulator upon detecting an overflow detection signal, then the modulator is restored from oscillation state, but excessive resetting occurs due to temporary overflows from noise
Solution Approach 1:
The system performs preliminary actions by calculating the overflow frequency and comparing it against a threshold before executing the reset operation. This preliminary analysis distinguishes between temporary overflows caused by noise and sustained overflows indicating true oscillation, thereby preventing premature or excessive resetting while ensuring restoration when actually needed.
Solution Approach 2:
The system implements feedback by continuously monitoring the overflow detection signal, calculating its frequency, and using this information to control the reset operation. The feedback loop compares the calculated overflow frequency against a predetermined threshold to dynamically determine whether resetting is appropriate, thus eliminating excessive resetting while maintaining reliable oscillation recovery.
2Measurement precision
If the microcomputer continuously monitors overflow detection signals to prevent excessive resetting, then operational accuracy improves, but the microcomputer burden increases
Solution Approach 1:
The system segments the oscillation detection function into dedicated hardware circuits including an overflow frequency calculation circuit and an oscillation judgment circuit. This segmentation offloads the complex monitoring and analysis tasks from the microcomputer to specialized hardware modules, thereby maintaining high detection accuracy while significantly reducing the microcomputer's processing burden.
Solution Approach 2:
The invention introduces an intermediary oscillation judgment circuit that acts as a mediator between the overflow detection signal and the microcomputer. This intermediary hardware circuit performs the complex frequency calculation and threshold comparison operations, translating raw overflow signals into simplified oscillation state information that the microcomputer can easily process, thus improving accuracy without increasing microcomputer burden.
3Manufacturing precision
If the ΔΣ modulator uses second order or more with cascade-connected integrators, then conversion performance improves, but oscillation occurs in response to large input signals or steeply varying signals
Solution Approach 1:
The system employs feedback by continuously monitoring the overflow detection signal generated by the integrators and using this information to control the reset operation. The feedback mechanism calculates the frequency of overflow events and compares it against a threshold to determine when oscillation has occurred, enabling the system to maintain high conversion performance while automatically restoring stability when oscillation is detected.
Solution Approach 2:
The invention utilizes parameter changes by dynamically adjusting the reset operation based on the calculated overflow frequency. When the frequency exceeds a predetermined threshold, the system changes the state of the modulator by triggering a reset, thereby adapting to varying input conditions and maintaining stability without compromising conversion performance during normal operation.
Data Source
AI summary
A semiconductor device comprises an overflow detection circuit (5) which compares an output of at least one integrator in a ΔΣ modulator (13) with a predetermined value to output an overflow detection signal; an overflow frequency calculation circuit (6) which calculates an overflow frequency value that is the frequency of the output from the integrator being outside a normal range, based on the overflow detection signal, and outputs the overflow frequency value; an oscillation judgment circuit (7) which judges whether the ΔΣ modulator (13) is in the oscillation state or not based on the overflow frequency value; and an oscillation halt circuit which suppresses oscillation of the ΔΣ modulator (13) when the oscillation judgment circuit (7) judges that the ΔΣ modulator is in the oscillation state; wherein it is determined whether the output of the integrator is temporarily outside the normal range due to noise or the like or the output of the integrator is outside the normal range due to oscillation, by obtaining the frequency with which the output of the integrator is outside the normal range, and the oscillation of the ΔΣ modulator (13) is suppressed only when it is oscillated.