Delta-Sigma Modulator Delay Compensation With Predictive Feedback

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Solution Overview

Problem

Continuous-time delta-sigma modulators face instability due to propagation delays through comparators, which degrade the performance of the feedback loop and can cause the modulator to be unstable.

Innovation Solution

The introduction of compensation capacitors and additional current DACs to create a third feedback loop that compensates for the comparator delay, stabilizing the system by injecting current into nodes between the integrator and comparator, and using pre-amplifiers to manage the feedback signals effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a comparator is used in the delta-sigma modulator feedback loop, then the modulator can perform analog-to-digital conversion, but the propagation delay through the comparator degrades feedback loop performance and causes instability

Engineering Contradiction:
Improvemodulator stabilityVSAvoidcomparator propagation delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by predicting the current comparator output based on previous comparator outputs and injecting this predicted value into the integrator before the actual delayed feedback arrives. This predictive feedback mechanism compensates for the propagation delay by providing the integrator with an estimate of what the feedback should be, thereby maintaining stability without requiring the delayed actual feedback signal.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If propagation delay through the comparator is reduced, then feedback loop performance improves, but additional compensation circuitry is required

Engineering Contradiction:
Improvefeedback loop performanceVSAvoidcompensation circuitry
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements feedback by using a delay element that stores previous comparator outputs and feeds them back through a predictor to generate the predicted current output. This feedback mechanism allows the system to compensate for propagation delay by continuously incorporating historical comparator output information into the predictive feedback signal injected into the integrator.

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration stabilizes the delta-sigma modulator by reducing the impact of comparator delays, enhancing the performance of the feedback loop and maintaining system stability.

Implementation Method 1

A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS11115044B2Loop delay compensation in a delta-sigma modulator
Publication Date: 2021.09.07 TEXAS INSTRUMENTS INC
  • US11115044B2 patent drawing
  • US11115044B2 patent drawing

AI summary

A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor has a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.