Delta-Sigma DAC Pulse Patterns for Linear Output Filtering
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Solution Overview
Problem
Delta-sigma D/A converters face challenges in achieving precise digital-to-analog conversion with high linearity due to the need for complex analog filtering and error correction, especially when the frequency of the output signal varies widely, leading to distortion and errors in the conversion of digital values to analog signals.
Innovation Solution
The delta-sigma D/A converter generates a binary, clock signal time discrete output signal by serially arranging signal patterns with the same number of edges, reducing the frequency range and allowing for simpler low-pass filtering and constant error correction, ensuring accurate representation of input values across a wide range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the output signal frequency varies widely to represent different input values, then the dynamic range of the converter is improved, but the filter characteristic deteriorates and conversion precision worsens
Solution Approach 1:
The patent changes the frequency parameter of the output signal by using different pulse width modulation patterns. Instead of varying frequency to represent different input values, the system maintains a constant frequency and varies the pulse width (duty cycle) within each period, thereby resolving the contradiction between dynamic range and filter characteristic
Solution Approach 2:
The patent employs periodic pulse patterns where each period contains a fixed number of clock cycles. The output signal consists of periodic sequences of high and low states with consistent timing structure, which allows the low-pass filter to operate at its optimal frequency point while still representing different input values through varying pulse widths within each period
2Reliability
If complex analog low-pass filters are used to handle wide frequency variations, then the filter characteristic is improved, but the device complexity increases
Solution Approach 1:
The patent transforms the frequency-varying signal into a constant-frequency signal by using periodic pulse patterns with fixed timing. This parameter change allows the use of simple, fixed-frequency low-pass filters instead of complex adaptive filters, thereby reducing device complexity while maintaining reliable filtering performance
Solution Approach 2:
Instead of adapting the filter to handle frequency variations, the patent inverts the approach by making the signal frequency constant and adapting the signal pattern (pulse width) to represent different input values. This inversion simplifies the filter design significantly
3Ease of operation
If edge distortion occurs in the output signal, then the ease of operation is improved, but the manufacturing precision deteriorates
Solution Approach 1:
The patent applies preliminary correction by pre-calculating and storing compensation values in a lookup table. The edge distortion characteristics are measured in advance, and correction data is prepared beforehand to compensate for the distortion during normal operation, thereby maintaining conversion linearity without complicating the real-time signal generation process
Data Source
AI summary
A delta-sigma D/A converter, by which a digital valued, input signal is convertible into a binary, clock signal time discrete, output signal. By forming an average value of the output signal over a number of clock signal cycles, an analog value of the input signal can be displayed. The delta-sigma D/A converter is embodied in such a manner that, in use, it provides the output signal by serial arrangement of signal patterns of a set of signal patterns, wherein the signal patterns of the set are, in each case, binary, clock signal time discrete and extend over a signal pattern cycles total of a plurality of clock cycles. At least two signal patterns of the set have mutually different signal pattern average values, which are formed over the respective signal pattern cycles total, and all signal patterns of the set have, in each case, essentially the same number, especially exactly the same number, of edges.