Delta-Sigma Modulator Self-Calibration for Fast RC Coefficient Trimming
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Solution Overview
Problem
Continuous-time delta-sigma modulators face challenges with calibration due to process variations, leading to inaccurate and time-consuming calibration procedures, especially when using active-RC integrators, which are sensitive to fabrication gradients and area constraints.
Innovation Solution
A method is introduced where the delta-sigma modulator enters a test mode to directly measure loop filter parameters, allowing for effective calibration of coefficients by configuring integrators as gain stages and using a digital chain with analog integrators, facilitating a trimming procedure that accounts for variations in coefficients and voltage references, and employing a simple digital state machine for the SAR search algorithm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If calibration is performed using an auxiliary circuit located far from the modulator loop filter, then calibration can be implemented, but the calibration procedure becomes sensitive to gradients in fabrication variables and measurement accuracy deteriorates
Solution Approach 1:
The patent merges the calibration function with the modulator loop filter by integrating calibration circuitry directly into the loop filter structure. This eliminates the need for separate auxiliary circuits located far from the modulator, thereby reducing sensitivity to fabrication gradients and improving measurement accuracy while maintaining ease of calibration implementation.
Solution Approach 2:
The patent introduces test signal injection points and measurement nodes as intermediaries within the loop filter to enable direct measurement of RC time constants. These intermediaries facilitate accurate calibration by providing direct access to critical parameters without requiring external auxiliary circuits, thus improving measurement precision.
2Ease of manufacture
If an auxiliary circuit is used to extrapolate RC time constant, then calibration can be performed, but area constraints prevent accurate replica of the RC network
Solution Approach 1:
The patent makes the loop filter serve dual functions: normal signal processing and calibration measurements. By integrating calibration circuitry into the existing loop filter structure and using the same RC networks for both signal filtering and calibration measurements, the patent eliminates the need for separate auxiliary calibration circuits, thereby saving chip area while maintaining calibration capability.
Solution Approach 2:
The loop filter performs self-calibration by using its own internal RC networks and components for measurement. The calibration circuitry leverages the existing loop filter structure, capacitors, and resistors to measure RC time constants without requiring external auxiliary circuits, thus eliminating area overhead while enabling accurate calibration.
3Ease of manufacture
If conventional calibration methods are used, then calibration can be performed, but calibration time becomes excessively long
Solution Approach 1:
The patent performs preliminary measurements of RC time constants directly within the loop filter structure before final calibration adjustments. By pre-measuring the RC parameters using integrated test modes and using these measurements to guide subsequent calibration steps, the patent reduces the overall calibration time while maintaining accuracy.
Solution Approach 2:
The patent implements periodic test modes that rapidly measure RC time constants at different operating conditions. By using periodic excitation signals and measurements taken during normal operation intervals, the patent enables fast calibration without requiring extended dedicated calibration time, thus reducing total calibration time while maintaining ease of implementation.
Data Source
AI summary
A delta-sigma modulator includes a quantizer, a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer, and a feedback network including a plurality of digital-to-analog converters. In a calibration mode of operation, a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal including a periodic alternated digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators, integrators of the plurality of cascaded integrators other than the first integrator operate in a gain mode of operation, the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal including the periodic alternated digital sequence, and calibration circuitry generates a calibration signal based on the digital test signal and a reference digital word.