Delta-Sigma Modulator Self-Calibration for RC Integrator Variations

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Continuous-time delta-sigma modulators face challenges in calibration due to process variations affecting RC integrators, which are often inaccurate and time-consuming, and require area-efficient solutions that account for variations in voltage references and parasitic capacitances.

Innovation Solution

A self-calibration technique for delta-sigma modulators that enters a test mode to directly measure loop filter parameters, using a digital chain and analog integrators configured as gain stages, with a digital state machine for SAR search, and incorporates dithering and chopping to enhance accuracy and reduce calibration time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If RC integrators are used in continuous-time delta-sigma modulators, then the modulator achieves low noise and reduced power consumption, but process variations cause calibration inaccuracies and require time-consuming calibration procedures

Engineering Contradiction:
Improvemodulator performance stabilityVSAvoidcalibration time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements self-calibration by configuring the modulator to operate in open-loop mode during test operations, where the system automatically measures and adjusts its own parameters without external intervention. The calibration circuitry uses the modulator's existing components (integrators, quantizer, DAC) to perform self-diagnosis and self-adjustment, eliminating the need for manual calibration and reducing calibration time significantly.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent changes the operating parameters of the modulator components during calibration by adjusting the feedback capacitance values and operating points of the integrators. By dynamically modifying these parameters during test mode and then restoring them for normal operation, the system achieves accurate calibration while maintaining the low-noise, low-power characteristics of the original RC integrator design.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If calibration is performed outside the modulator loop using an auxiliary circuit, then calibration can be implemented, but the calibration becomes sensitive to fabrication gradients and area constraints reduce measurement accuracy

Engineering Contradiction:
Improvecalibration implementationVSAvoidcalibration accuracy
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

The patent merges the calibration function with the existing modulator loop structure by using the same integrators, quantizer, and DAC that are already present in the signal path. Instead of adding separate auxiliary calibration circuits, the calibration process utilizes the existing components in a reconfigured open-loop mode, thereby eliminating sensitivity to fabrication gradients and avoiding area constraints associated with additional calibration circuitry.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent makes the modulator components multi-functional by enabling them to serve both signal processing and calibration functions. The integrators can operate as integration elements during normal operation and as measurement elements during calibration, while the quantizer and DAC are used for both signal conversion and parameter measurement. This universal usage eliminates the need for dedicated calibration circuits and improves measurement accuracy.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If traditional calibration methods are used, then calibration can be performed, but the calibration procedure is time-consuming and may take seconds for each individual device

Engineering Contradiction:
Improvecalibration completenessVSAvoidcalibration throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements self-calibration that automatically adjusts parameters during brief test operations without requiring lengthy manual procedures. The system performs rapid measurements and adjustments using its own components, reducing calibration time from seconds to much shorter durations, thereby significantly improving production throughput while maintaining calibration completeness.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent performs preliminary calibration measurements during manufacturing test operations before final assembly, using the open-loop configuration to quickly assess and adjust parameters. By conducting calibration early in the manufacturing process and using efficient measurement techniques, the system reduces overall calibration time and improves productivity without sacrificing calibration accuracy.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4080771B1Self-calibration circuit for delta-sigma modulators, corresponding device and method
Publication Date: 2025.10.01 STMICROELECTRONICS SRL
  • EP4080771B1 patent drawingFigure 1~2B
  • EP4080771B1 patent drawingFigure 3A~4B
  • EP4080771B1 patent drawingFigure 4C~5

AI summary

A self-calibration arrangement is disclosed for, e.g., a Continuous-Time Delta-Sigma Modulator comprising a quantizer circuit (A/D, 14) to provide at an output node (DOUT) a digital signal resulting from analog-to-digital conversion of an analog input signal at an input node (VIN), a plurality of integrator circuits (1/s); 121, 122) cascaded in a signal propagation path from the input node (VIN) to the quantizer circuit (A/D, 14), as well as a feedback network (16) comprising a plurality of digital-to-analog converters (131, 132; D/A1, D/A2) each coupled to a respective integrator circuit (1/s; 121, 122) in the signal propagation path from the input node (VIN) to the quantizer circuit (A/D, 14). The circuit is configured to be switched to a test mode during which the converter (131; D/A1) coupled to the first integrator circuit (121) is configured to receive a periodic alternated digital sequence (DS) while the integrator circuit or circuits (122) cascaded to the first is/are reconfigured as a gain stage (G2) with the digital-to-analog converter (132; D/A1) coupled therewith disabled. Comparator circuitry (18) is provided to receive a comparison signal (DAVG) which is a function of the digital signal (DOUT) provided at the output node for comparison with a target digital word (DTGT). The comparator circuitry (18) produces (184) a digital calibration signal (CTRIM) as a function of the difference (183) between the comparison signal (DAVG) and the target digital word (DTGT).