Delta-Sigma Modulator Architecture With a Single-Adder Critical Path

The patent extracts and removes adders from the critical signal path. Specifically, the design uses a segmented accumulator where the least significant bit (LSB) accumulator is separated from the most significant bit (MSB) accumulator, and the LSB adder is removed from the critical path entirely. This extraction eliminates the delay contribution of the LSB adder and multiplexer from the critical path, enabling higher operating frequencies while maintaining fraction generation accuracy through the segmented architecture.

The patent divides the accumulator into segmented stages - specifically separating the LSB accumulator from the MSB accumulator. This segmentation allows different parts of the accumulator to operate independently with different timing requirements. The LSB accumulator can be updated faster without constraining the overall critical path, as its results are combined with the MSB accumulator in a non-critical path manner, thus improving operating frequency while preserving functional accuracy.

The patent extracts multiplexers from the critical path by implementing a dedicated LSB accumulator that updates independently. The select logic for choosing between different accumulator outputs is removed from the critical path, as the segmented architecture allows the LSB accumulator to always provide its output without requiring multiplexing selection in the timing-critical path. This maintains operational versatility while enabling higher clock frequencies.

The patent segments the accumulator architecture into LSB and MSB portions that can operate with different timing characteristics. The LSB segment can complete its operations faster and feed into the MSB segment without creating a long sequential chain. This segmentation reduces the total number of sequential logic elements in the critical path while preserving the ability to perform complex fractional operations through the coordinated operation of segmented stages.