Delta-Sigma Modulator Timing for Zero-Point Shifting and Double Sampling

The patent changes the parameter of loop filter order from high (3rd order or more) to low (2nd order or less) while compensating for the signal-to-noise ratio through zero-point shifting technique. This parameter change resolves the contradiction by achieving the desired signal-to-noise ratio through a different mechanism (zero-point scattering) rather than increasing filter order, thereby reducing consumption current.

The patent introduces zero-point shifting as an intermediary technique to achieve signal-to-noise ratio improvement without increasing filter order. By scattering zero points of the noise transfer function on the unit circle through local feedback, the patent achieves the desired performance without the penalty of increased consumption current associated with higher order filters.

The patent dynamically adjusts the delay timing of the local feedback path to be half a clock period, which is different from the conventional single sampling timing. This dynamic timing adjustment allows the system to accommodate both zero-point shifting and double sampling simultaneously, resolving the timing conflict without increasing device complexity.

The patent implements double sampling by utilizing two non-overlapping clock phases (φ1 and φ2) to perform sampling operations at different time periods. This periodic action with half-clock-period delay enables the system to execute both zero-point shifting and double sampling operations in a coordinated manner, avoiding timing conflicts.