Delta-Sigma Modulator Timing to Prevent Feedback Factor Loss
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Solution Overview
Problem
Conventional ΔΣ modulation type A/D converters face accuracy issues due to overlapping holding periods in the sampling and DAC capacitors, which lower the feedback factor and amplifier gain, resulting in reduced calculation accuracy.
Innovation Solution
A ΔΣ modulator configuration with a control circuit that manages non-overlapping holding periods for the sampling and DAC capacitors, preventing simultaneous electrical connection and maintaining a larger feedback factor, thereby enhancing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the holding periods of the sampling capacitor and DAC capacitor overlap, then the circuit operation is simplified, but the feedback factor is reduced and amplifier gain is lowered, resulting in reduced calculation accuracy
Solution Approach 1:
The patent implements dynamic control of capacitor connections by using control signals to switch between different operational modes. The sampling capacitor and DAC capacitor are dynamically connected or disconnected based on the operational phase, ensuring that their holding periods do not overlap. This dynamic switching mechanism allows the system to maintain high feedback factor and amplifier gain during critical periods while simplifying operation during other periods.
Solution Approach 2:
The patent employs periodic action by dividing the operational cycle into distinct phases where the sampling capacitor and DAC capacitor operate in alternating periods. The holding periods are structured to be non-overlapping within each cycle, with the sampling capacitor holding during the sampling phase and the DAC capacitor holding during the DAC phase. This periodic separation ensures that the feedback factor remains high while maintaining manageable circuit operation.
2Measurement precision
If the holding periods of the sampling and DAC capacitors are made non-overlapping, then the feedback factor is maintained and amplifier gain is improved, but the control circuit complexity increases
Solution Approach 1:
The patent uses feedback mechanisms where the quantization result from the previous cycle influences the control signals for the current cycle. The control circuit generates phase control signals based on the quantization results, creating a feedback loop that automatically coordinates the holding periods of the sampling and DAC capacitors. This feedback-based control ensures non-overlapping holding periods while keeping the control logic systematic and manageable.
Solution Approach 2:
The control circuit is designed to automatically generate the necessary control signals based on the quantization results and operational phase, without requiring external intervention. The system self-regulates the holding periods of both capacitors through internal logic that ensures non-overlapping operation. This self-service capability reduces the need for complex external control mechanisms while maintaining high calculation accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution prevents the lowering of accuracy caused by feedback factor reduction, allowing for a larger amplifier gain and improved calculation accuracy by ensuring non-overlapping holding periods for the sampling and DAC capacitors.
Implementation Method 1
an analog input voltage is sampled by a sampling capacitor, and a charge of the charged sampling capacitor is transferred to an integration capacitor
Implementation Method 2
a charge of the charged sampling capacitor is transferred to an integration capacitor connected between input and output terminals of an amplifier
Implementation Method 3
A DAC capacitor is provided in a portion where a D/A converter outputs an analog voltage as a result of quantization of an output voltage of the amplifier
Data Source
AI summary
A ΔΣ modulator includes an input circuit having a sampling capacitor, an integration circuit, a quantizer and a D/A converter having a DAC capacitor. The input circuit takes in an analog input voltage in the sampling capacitor in a sampling period, and transfers a charge to the integration circuit in a holding period. The D/A converter takes in an analog potential, to which selection switches are connected in the sampling period based on a digital output of the quantizer, in the DAC capacitor, and subtracts a charge from the integration circuit in the holding period. At this time, since the input circuit and the D/A converter are set so that the holding periods do not overlap with each other, an error caused by the lowering of a feedback factor is suppressed.


