Delta Arrangement Active Matrix Substrate Reducing Parasitic Capacitance
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Solution Overview
Problem
Conventional LCD panels with a strip arrangement of color filtering films result in lower spatial resolution and increased parasitic capacitance due to the proximity of transmissive conductive electrodes to data lines, leading to display quality issues and cross-talk, especially when overlay shifts occur during fabrication.
Innovation Solution
An active matrix substrate with a delta arrangement of sub-pixels, where each data line controls sub-pixels for a single color, and includes symmetric or mirror-symmetric turnings, with pixel electrodes extending over data lines to maintain equal overlay areas, reducing parasitic capacitance and cross-talk by employing a dielectric layer with a low dielectric constant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If sub-pixels are arranged in strip arrangement with color filtering films, then the structure is simple and easy to manufacture, but spatial resolution is reduced and parasitic capacitance increases
Solution Approach 1:
The patent applies asymmetric arrangement by transitioning from traditional strip arrangement to delta arrangement of sub-pixels. In the delta arrangement, sub-pixels of the same color are positioned at asymmetric locations relative to data lines, which reduces parasitic capacitance and improves spatial resolution while maintaining manufacturing feasibility through symmetric turnings design
2Device complexity
If transmissive conductive electrodes are placed close to data lines, then device complexity is reduced, but parasitic capacitance increases causing cross-talk
Solution Approach 1:
The patent uses asymmetric positioning of sub-pixels in delta arrangement relative to data lines, combined with symmetric turnings in data line routing. This asymmetric-symmetric combination reduces the overlay area between transmissive conductive electrodes and data lines, thereby reducing parasitic capacitance and cross-talk while maintaining structural simplicity
Solution Approach 2:
The patent introduces symmetric turnings in the data line routing to create equal overlay areas on both sides of sub-pixels. This dimensional adjustment in the routing path compensates for the proximity issue, reducing net parasitic capacitance through geometric cancellation while keeping the overall structure simple
3Manufacturing precision
If overlay shift occurs during fabrication, then manufacturing tolerance is relaxed, but parasitic capacitance becomes unequal causing display quality degradation
Solution Approach 1:
The patent pre-designs symmetric turnings in the data line routing that create equal overlay areas on both sides of each sub-pixel. This preliminary symmetric configuration ensures that even if overlay shifts occur during fabrication, the parasitic capacitances remain equal, preventing display quality degradation and maintaining reliability
Solution Approach 2:
The symmetric turnings design acts as a cushioning mechanism against overlay shifts. By creating equal overlay areas in advance, the design compensates for potential fabrication variations, ensuring that parasitic capacitance imbalance does not occur even when alignment tolerances are exceeded
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The delta arrangement improves display performance by reducing parasitic capacitance and maintaining equal overlay areas, minimizing cross-talk and enhancing aperture ratio, while allowing for better light mixing and uniform color display.
Implementation Method 1
parasitic capacitance Cpd caused between the transmissive conductive electrodes 244 and the data lines 230
Implementation Method 2
employing a dielectric layer with a low dielectric constant
Data Source
AI summary
An active matrix substrate including a substrate, a plurality of scan lines, a plurality of data lines and a plurality of sub-pixels is provided. The scan lines and the data lines are disposed on the substrate, and define a plurality of sub-pixel regions distributed in a delta arrangement. The sub-pixels corresponding to the sub-pixel regions are disposed on the substrate. The sub-pixels are electrically connected with corresponding scan lines and corresponding data lines. Between two sub-pixel regions corresponding to any two adjacent sub-pixels at a same side of one scan line, there are two data lines. Each sub-pixel includes an active device and a pixel electrode. The active device is electrically connected with a corresponding scan line and a corresponding data line. The pixel electrode is electrically connected with the active device, and extends from the sub-pixel region corresponding to the sub-pixel to a position over the data line.