Demand-adaptive Memory Compression for CTE Cache Miss Reduction
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Solution Overview
Problem
Existing hardware memory compression technologies suffer from high address translation overheads, particularly for large and irregular workloads, due to fine-grained block-level translations and CTE misses, which increase latency and reduce efficiency.
Innovation Solution
Implementing demand-adaptive memory compression by compressing only cold pages and embedding CTEs into PTBs to enable page-level translations, reducing CTE cache misses and parallelizing data access with CTE access to hide latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fine-grained block-level translations are used for memory compression, then compression capability is improved, but address translation overhead increases
Solution Approach 1:
The patent divides the memory management space into two distinct segments: cold pages that undergo compression and hot pages that remain uncompressed. This segmentation allows the system to apply compression selectively only where beneficial, avoiding the translation overhead associated with compressing frequently accessed data. The page table is similarly segmented with separate handling for cold and hot pages, enabling fine-grained control over where compression is applied.
Solution Approach 2:
The patent implements local quality by applying different compression strategies to different regions of memory based on access patterns. Cold pages in less frequently accessed memory regions are compressed to maximize space utilization, while hot pages in frequently accessed regions remain uncompressed to minimize translation overhead. This localized approach ensures that compression is applied only where it provides net benefit.
2Speed
If CTE cache is used for address translation, then translation speed is improved, but CTE cache misses increase latency
Solution Approach 1:
The patent performs preliminary actions by pre-loading CTEs into the page table during page allocation and initial access. When a page is first accessed, its CTE is immediately populated and cached, so that subsequent accesses to the same page do not require cache lookups. This preliminary population of the page table reduces the likelihood of CTE cache misses during normal operation.
Solution Approach 2:
The patent implements dynamic adaptation by monitoring access patterns and adjusting compression status accordingly. Pages that transition from cold to hot status are dynamically uncompressed and their CTEs are updated in the page table, while pages remaining cold continue to use compressed representation with CTE cache lookups. This dynamic behavior allows the system to adapt to changing workload patterns.
3Quantity of substance
If all pages are compressed to increase memory capacity, then memory capacity is improved, but decompression latency increases
Solution Approach 1:
The patent applies partial compression by compressing only cold pages rather than all pages in memory. This partial action approach achieves a significant portion of the potential memory capacity improvement (by compressing the minority of cold pages) while avoiding the excessive decompression latency that would result from compressing all pages including frequently accessed hot pages.
Solution Approach 2:
The patent changes the compression parameter dynamically based on page access characteristics. Cold pages are assigned a compressed representation with high compression ratio, while hot pages maintain an uncompressed representation with fast access. This parameter change allows the system to optimize for either capacity or speed depending on the specific page and its access pattern.
Data Source
AI summary
Various aspects of a computing system for dynamically managing storage of data in a memory are described. In one example, a computing system includes a memory having a plurality of memory levels and a processing circuit configured to dynamically manage storage of data in the memory based on instructions received from an operating system (OS). To dynamically manage storage of the data, the processing circuit is further configured to determine a first memory level and a second memory level, where the first memory level is used to store uncompressed pages and the second memory level is used to store compressed pages. The processing circuit is further configured to determine a free list of free pages in the first memory level or the second memory level and store a page associated with the data in the first level or the second level based at least in part on the free list.