Dematching Layer Extension for ASIC Protection in Transducer Arrays
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Solution Overview
Problem
The interconnection of multidimensional transducer arrays with electronics is challenging due to limited space for separate electrical connections, mechanical stress on ASICs during the transducer formation process, and inconsistencies in electrical pitches caused by chip shifting during the die attach process, which affects the reliability of flex-to-ASIC connections.
Innovation Solution
A dematching layer is used to extend beyond the footprint of the transducer array, providing a rigid and conductive substrate for direct connection to the ASIC and supporting the acoustic stack, while also acting as an electrical routing layer for signal and ground connections, allowing for low-temperature asperity contact and reducing the risk of mechanical stress and contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ASIC is placed directly on the acoustic array with flip-chip connections, then the electrical connection between ASIC and acoustic elements is achieved, but the ASIC is exposed to mechanical stress and chemicals during transducer formation process causing chip cracking
Solution Approach 1:
A protective layer is introduced as an intermediary between the ASIC and the acoustic array. This protective layer shields the ASIC from mechanical stress and chemical exposure during the transducer formation process, while still allowing electrical connections to be established through it. The intermediary layer thus resolves the contradiction by protecting the ASIC without preventing electrical connection.
Solution Approach 2:
The protective layer is applied beforehand to cushion the ASIC against upcoming mechanical stress and chemical exposure during subsequent processing steps. This prior cushioning prevents chip cracking before it can occur, addressing the harmful factors in advance while maintaining connection reliability.
2Productivity
If chip tiling is performed during die attach process, then multiple ASICs are connected to the acoustic array, but chip shift or off-set occurs causing inconsistent electrical pitches
Solution Approach 1:
The protective layer serves as an intermediary that compensates for chip shift during the die attach process. By providing a compliant interface, it allows for adjustment and realignment, thereby maintaining consistent electrical pitches even when chip positioning varies slightly, thus resolving the contradiction between productivity and manufacturing precision.
3Reliability
If flex-to-ASIC connections are made after acoustic build process, then the connection process temperature is limited to 100°C or lower, but the ASIC uneven surface requires higher temperature for good electrical connection
Solution Approach 1:
The protective layer acts as an intermediary that enables good electrical connection at lower temperatures. Its material properties facilitate effective thermal and electrical contact between the flex cable and the uneven ASIC surface without requiring high temperature processes, thus resolving the contradiction between connection reliability and temperature requirements.
4Reliability
If larger pads are used for flex-to-ASIC connections, then reliable electrical connections are achieved despite flex circuit dimensional instability, but the keep-out distance increases reducing available space
Solution Approach 1:
The protective layer serves as an intermediary that enables reliable electrical connections with smaller pads. By providing a compliant and conductive interface, it compensates for flex circuit dimensional instability without requiring large pad areas, thus resolving the contradiction between connection reliability and available space.
Data Source
AI summary
For direct chip-on-array for a multi-dimensional transducer array, the generally rigid and conductive dematching layer is extended beyond a footprint of the transducer array. The ASIC is directly connected to the dematching layer on one side, while the other side provides for electrical connection to the elements of the array and I/O pads for connections (e.g., flex-to-dematching layer) to the ultrasound imaging system. By using the dematching layer rigidity, the ASIC may be protected during formation of the acoustic stack. By using the dematching layer conductivity, any mis-alignment is compensated by the routing through the dematching layer, and/or a large flat region is provided for I/O, allowing for good low temperature asperity contact connections with larger area than flip-chip solder bumps. By providing the I/O for the system connections on a different side of the dematching layer than the ASIC, a large keep-out distance due to underfill may be avoided.