Demodulation Circuit for Digital Isolator Common Mode Transient Immunity
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Solution Overview
Problem
Digital isolators face challenges in addressing common mode transient immunity (CMTI) due to sudden voltage spikes or fluctuations between grounds of isolation barriers, leading to errors and glitches in signal transmission.
Innovation Solution
A demodulation circuit employing a waveform regulator, first and second counters, and an SR latch to generate regulated modulation signals, count cycles, and trigger the SR latch to pull up or down the demodulated output signal, effectively ignoring noise caused by common mode transients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional demodulation circuits are used in digital isolators, then the circuit structure is simple, but the common mode transient immunity (CMTI) is poor due to voltage spikes causing errors and glitches
Solution Approach 1:
The demodulation circuit is divided into multiple functional modules: a first counter for counting modulation signal cycles, a second counter for counting reference clock cycles, and an SR latch for signal output. This segmentation allows each module to perform a specific function, improving CMTI by systematically addressing transient voltage issues while maintaining manageable circuit complexity
Solution Approach 2:
The circuit performs preliminary counting of signal cycles before generating the demodulated output. The counters accumulate cycle information over time and only trigger the SR latch when predetermined counting conditions are met, allowing the circuit to anticipate and filter out transient voltage spikes before they cause errors
2Reliability
If cycle counting is performed to filter common mode transients, then the common mode transient immunity is improved, but the response time increases due to counting requirements
Solution Approach 1:
The circuit changes the parameter of counting threshold by configuring the counters to trigger the SR latch only when specific cycle counts are reached. This parameter adjustment allows the circuit to differentiate between legitimate modulation signals and transient noise, improving reliability while controlling response time through optimized counting values
3Manufacturing precision
If counters and SR latch are added to regulate modulation signals, then glitches are reduced in demodulated output, but the device complexity increases
Solution Approach 1:
The first counter, second counter, and SR latch are merged into a single integrated demodulation circuit block that processes the modulation signal in one unified structure. This merging reduces the overall device complexity compared to having separate independent circuits, while still achieving glitch reduction through the coordinated operation of the combined components
Data Source
AI summary
The demodulation circuit includes a waveform regulator, a first counter, a second counter, and an SR latch. The waveform regulator generates a regulated modulation signal according to a pair of differential isolated modulation signals, which is generated according to a modulation of an input data signal with a carrier clock signal. The first counter counts cycles of the regulated modulation signal so as to generate a set signal. The second counter counts cycles of a reference clock signal so as to generate a reset signal. The SR latch includes a set terminal for receiving the set signal, a reset terminal for receiving the reset signal, and an output terminal for outputting a demodulated output signal. The SR latch is triggered by the set signal to pull up the demodulated output signal, and is triggered by the reset signal to pull down the demodulated output signal.