Demodulation Circuit Variable Clock Speed Fixed Packet Generation
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Solution Overview
Problem
Conventional demodulation circuits face challenges in generating fixed-length packets from variable-length packets without increasing buffer memory, particularly when clock frequency conversion is required for transmission at a fixed clock frequency.
Innovation Solution
A demodulation circuit that embeds a header section in split TLV packets and adjusts the clock signal switching speed between L and H levels, setting it twice for the first data compared to subsequent data, allowing for the conversion of variable-length TLV packets into fixed-length packets without the need for clock frequency conversion or additional buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If clock frequency conversion is performed to generate fixed-length packets by splitting variable-length packets, then fixed-length packet generation is achieved, but buffer memory size increases
Solution Approach 1:
The patent applies dynamics by making the clock signal period variable rather than fixed. The control unit dynamically adjusts the clock signal period based on whether the current data is header data or payload data, creating a dynamic packet transmission system that adapts to different data types without requiring buffer memory for frequency conversion
Solution Approach 2:
The patent changes the time parameter (clock signal period) to differentiate between header and payload data transmission. By setting the clock period to a first value for header data and a second value for payload data, the system achieves packet length uniformity through parameter variation rather than through buffer-based frequency conversion
2Adaptability or versatility
If header packets are inserted into fixed-length packets for variable-length packet transmission, then compatibility with conventional back-end processing circuits is achieved, but device complexity increases
Solution Approach 1:
The patent achieves universality by making the clock signal serve multiple functions: it both transmits data and encodes data type information (header vs. payload) through period variation. This multi-functionality eliminates the need for separate header insertion mechanisms and complex packet processing logic while maintaining compatibility with conventional back-end processing circuits
Data Source
AI summary
Disclosed is a transmitter that includes a demodulation circuit and a transmitting-side back-end processing circuit. When a TLV packet superimposed on a broadcast wave and transmitted with a variable data length is to be converted to split TLV packets with a fixed data length, the demodulation circuit sets a speed for switching between L and H levels of a clock signal in such a manner that the speed for first data including a packet header to be embedded in a header section of the split TLV packets is twice the speed for data subsequent to the first data. The transmitting-side back-end processing circuit QAM-modulates a signal demodulated by the demodulation circuit for cable broadcasting purposes.