Digital Radio Demodulator Buffer Control for Asynchronous Data Flow
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Solution Overview
Problem
Existing radio receivers face challenges in maintaining data flow requirements due to asynchronous clock domains between integrated circuits, leading to buffer overflow or underflow issues when using synchronous data interfaces.
Innovation Solution
Implementing a control loop system that includes a sample rate converter, buffer, and digital demodulator to synchronize data flow, using a target size value to prevent buffer overflow or underflow by adjusting the sample rate based on feedback mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a synchronous data interface is used to communicate between integrated circuits, then data transfer reliability is improved, but buffer overflow or underflow issues occur due to clock domain differences
Solution Approach 1:
The patent introduces an asynchronous FIFO buffer as an intermediary component between the tuner circuit and demodulator circuit. This buffer acts as a mediator that decouples the two clock domains, allowing data to be transferred reliably without causing buffer overflow or underflow. The buffer absorbs clock domain differences by accepting data at one rate and outputting at another rate, eliminating the harmful effects of synchronous interface constraints.
Solution Approach 2:
The patent changes the operational parameters of the data interface by transitioning from a synchronous interface to an asynchronous interface. This parameter change allows the system to accommodate different clock rates between integrated circuits. The control loop dynamically adjusts the target size value parameter to optimize buffer utilization and prevent overflow/underflow while maintaining reliable data transfer.
2Stability of the object's composition
If the clock rate of the OFDM demodulator is changed to synchronize data flow, then buffer stability is improved, but system complexity and timing requirements increase
Solution Approach 1:
The patent segments the data flow synchronization function into a separate control loop module that operates independently from the main OFDM demodulator. The control loop monitors buffer depth and dynamically adjusts the target size value, while the demodulator continues operating at its fixed clock rate. This segmentation maintains buffer stability without requiring changes to the demodulator's clock rate, thereby avoiding increased system complexity.
Solution Approach 2:
The patent implements a feedback mechanism where the control loop continuously monitors the buffer depth and uses this information to adjust the target size value. This feedback ensures buffer stability by preventing both overflow and underflow conditions. The feedback loop operates independently without affecting the demodulator's clock rate, thus maintaining system simplicity while achieving stable buffer operation.
3Adaptability or versatility
If a buffer is introduced to handle asynchronous data flow, then adaptability between clock domains is improved, but risk of buffer overflow or underflow increases
Solution Approach 1:
The patent makes the buffer operation dynamic by introducing a control loop that continuously adjusts the target size value based on current buffer depth. Instead of using a fixed buffer size, the system dynamically adapts the fill level to match the actual data flow requirements. This dynamic adjustment maintains high adaptability between clock domains while minimizing the risk of overflow or underflow by optimizing buffer utilization in real-time.
Solution Approach 2:
The control loop provides continuous feedback on buffer depth and uses this information to adjust the target size value, creating a self-regulating system. When the buffer approaches full capacity, the control loop reduces the target size to prevent overflow. When the buffer is nearly empty, it increases the target size to prevent underflow. This feedback mechanism maintains reliability while preserving adaptability between different clock domains.
Data Source
AI summary
Systems and methods for asynchronous data flow in digital radios are provided. In one aspect, a demodulator circuit includes a receiver circuit configured to receive: a plurality of samples of a radio frequency signal received from a tuner, a clock, and a target size value, the receiver circuit further configured to output the samples at a first rate based on the target size value. The demodulator circuit also includes a sample rate converter configured to receive the samples from the receiver circuit and output the samples at a second rate based on a rate offset value, and a buffer configured to receive the samples from the sample rate converter and output the samples. The demodulator circuit further includes a digital demodulator configured to receive the samples from the buffer and demodulate the samples, and a control loop configured to generate the target size value.