Drain Extended MOS Transistor Breakdown Voltage
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Solution Overview
Problem
DEMOS transistors are limited to high voltage applications below 15 volts due to their breakdown voltage limitations, necessitating a design enhancement to increase their operational voltage capacity.
Innovation Solution
A semiconductor topography with an extended drain contact region within a well region and dielectrically spaced extension regions between the well region and the channel region, featuring a higher net concentration of electrically active impurities in the drain contact region compared to the well region, which increases the breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the drain contact region is laterally displaced apart from the channel to create a drain extension region, then the breakdown voltage increases, but the on-resistance increases
Solution Approach 1:
The patent applies local quality by creating distinct doping regions with different impurity concentrations at different locations. The drain extension region has a first net concentration of electrically active impurities, while the drain contact region has a second net concentration that is higher. This gradual transition from lower to higher doping concentration locally optimizes each region: the lower-doped extension region maintains higher breakdown voltage, while the higher-doped contact region reduces on-resistance.
Solution Approach 2:
The patent changes the doping concentration parameter along the drain structure. By varying the net concentration of electrically active impurities from the drain extension region to the drain contact region, the patent achieves a compromise between breakdown voltage and on-resistance. The parameter gradient allows the structure to handle higher voltages while maintaining acceptable resistance characteristics.
2Strength
If the drain contact region is laterally displaced apart from the channel to create a drain extension region, then the breakdown voltage increases, but the transistor size increases
Solution Approach 1:
The patent addresses the size issue by utilizing vertical dimensionality through the well structure. The drain extension region and drain contact region are formed within a well that extends vertically into the substrate. This allows the lateral displacement to be achieved while confining the structure vertically, thereby reducing the overall footprint and minimizing the increase in transistor size.
3Reliability
If the net concentration of electrically active impurities is increased in the drain contact region, then the on-resistance decreases, but the breakdown voltage decreases
Solution Approach 1:
The patent applies local quality by creating distinct doping regions with different impurity concentrations at different locations. The drain extension region has a first net concentration of electrically active impurities, while the drain contact region has a second net concentration that is higher. This gradual transition from lower to higher doping concentration locally optimizes each region: the lower-doped extension region maintains higher breakdown voltage, while the higher-doped contact region reduces on-resistance.
Solution Approach 2:
The patent segments the drain structure into two distinct regions: the drain extension region and the drain contact region. Each segment serves a specific function - the extension region is optimized for voltage handling with lower doping, while the contact region is optimized for current conduction with higher doping. This segmentation allows each part to perform its function optimally without compromising the other.
Data Source
AI summary
A semiconductor topography and a method for forming a drain extended metal oxide semiconductor (DEMOS) transistor is provided. The semiconductor topography includes at least a portion of an extended drain contact region formed within a well region and a plurality of dielectrically spaced extension regions interposed between the well region and a channel region underlying a gate structure of the topography. The channel region of a first conductivity type and the well region of a second conductivity type opposite of the first conductivity type. In addition, the plurality of dielectrically spaced extension regions and the extended drain contact region are of the second conductivity type. Each of the plurality of dielectrically spaced extension regions has a lower net concentration of electrically active impurities than the well region. Moreover, the extended drain contact region has a greater net concentration of electrically active impurities than the well region.