Demosaic Noise Reduction Circuit for Lower CPU Bandwidth

Solution Overview

Problem

Existing image processing algorithms executed on central processing units (CPUs) consume significant bandwidth and increase power consumption, necessitating the development of hardware-based image processing pipelines for efficient noise reduction.

Innovation Solution

An image processing circuit with a noise reduction module that includes a pre-demosaic circuit, kernel calculation circuit, noise filtering circuit, and blending circuit, which performs demosaic-based noise reduction using adaptive denoising/de-mosaicking kernels and bilateral kernels to generate a de-noised image.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If image processing algorithms are executed on CPU, then image processing can be performed with flexibility, but CPU bandwidth consumption increases and power consumption increases

Engineering Contradiction:

Improveprocessing flexibilityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent segments the image processing function from the CPU by implementing a dedicated hardware image processing pipeline. The pipeline is divided into independent functional blocks (demosaic circuit, noise filtering circuit, blending circuit) that can process images independently of CPU intervention, thereby reducing CPU bandwidth consumption while maintaining processing flexibility through hardware configuration.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary hardware image processing pipeline between the image sensor and the CPU. This pipeline acts as a mediator that performs noise reduction and demosaic processing before data reaches the CPU, reducing the processing burden on the CPU while maintaining system flexibility through programmable processing stages.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If image processing algorithms are executed on CPU, then image processing can be performed with flexibility, but CPU bandwidth consumption increases

Engineering Contradiction:

Improveprocessing flexibilityVSAvoidCPU bandwidth

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent segments the image processing function from the CPU by implementing a dedicated hardware image processing pipeline. The pipeline is divided into independent functional blocks (demosaic circuit, noise filtering circuit, blending circuit) that can process images independently of CPU intervention, thereby reducing CPU bandwidth consumption while maintaining processing flexibility through hardware configuration.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary hardware image processing pipeline between the image sensor and the CPU. This pipeline acts as a mediator that performs noise reduction and demosaic processing before data reaches the CPU, reducing the processing burden on the CPU while maintaining system flexibility through programmable processing stages.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Use of energy by moving object

If hardware-based image processing pipeline is implemented, then power consumption is reduced and CPU resources are optimized, but device complexity increases

Engineering Contradiction:

Improvepower consumptionVSAvoidcircuit complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent merges multiple image processing functions (demosaic processing, noise filtering, and image blending) into a single integrated hardware pipeline. By combining these functions into one cohesive circuit structure with shared resources, the patent reduces overall device complexity compared to implementing separate independent circuits for each function, while still achieving power consumption reduction through hardware efficiency.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent implements universal processing circuits that can perform multiple functions. The noise filtering circuit, for example, can apply different filtering algorithms and parameters depending on the processing requirements. This multi-functionality reduces the need for separate dedicated circuits for each processing task, thereby reducing device complexity while maintaining the power consumption benefits of hardware implementation.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12602738B2Noise reduction circuit with demosaic processing

Publication Date: 2026.04.14 APPLE INC

AI summary

A noise reduction circuit that performs demosaic-based noise reduction on image data. The noise reduction circuit includes a pre-demosaic circuit, a kernel calculation circuit, a noise filtering circuit, and a blending circuit. The pre-demosaic circuit generates a de-mosaiced version of an image. The kernel calculation circuit generates a denoising kernel for at least one pixel of the image and a bilateral kernel for the at least one pixel of the image using the de-mosaiced version of the image. The noise filtering circuit performs noise filtering of the image using the denoising kernel to generate a first de-noised version of the image, and performs noise filtering of the image using the bilateral kernel to generate a second de-noised version of the image. The blending circuit blends the first de-noised version with the second de-noised version to generate an output de-noised version of the image.