Demultiplexer Circuit Layout for Display Uniformity
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Solution Overview
Problem
In display devices employing the Source Shared Driving (SSD) method with a narrow pixel pitch, the diagonal arrangement configuration of transistors in the demultiplexer circuit leads to adjacent data signal lines with significantly different lengths, causing uneven charge distribution and resulting in striped unevenness during monochrome displays.
Innovation Solution
The active matrix substrate is designed with a signal supply control circuit where connection control switching elements are grouped into sets with alternating shift directions in the vertical direction, ensuring that adjacent data signal lines have similar path layouts and charging rates, thereby minimizing the occurrence of striped unevenness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If transistors in the demultiplexer circuit are arranged in a diagonal configuration to accommodate narrow pixel pitch, then the device can be manufactured with smaller pixel dimensions, but adjacent data signal lines have significantly different lengths causing striped unevenness
Solution Approach 1:
The demultiplexer circuit is divided into multiple banks, with each bank handling a specific group of data signal lines. This segmentation allows independent optimization of transistor arrangement in each bank, enabling uniform path length control for adjacent lines while maintaining narrow overall pixel pitch through the distributed bank structure.
Solution Approach 2:
The patent transitions from a single diagonal arrangement to a multi-bank two-dimensional layout structure. By organizing demultiplexers into multiple banks arranged in both horizontal and vertical directions, the design achieves uniform signal path lengths through spatial distribution across multiple dimensions rather than relying on single-direction diagonal placement.
2Manufacturing precision
If transistors are arranged vertically with respect to data signal lines, then data signal lines have uniform lengths, but the transistor arrangement occupies excessive area preventing narrow pixel pitch implementation
Solution Approach 1:
The demultiplexer is segmented into multiple independent banks distributed across the substrate. Each bank handles a subset of data signal lines and can be compactly arranged, reducing the total area required compared to a single large vertical arrangement while maintaining uniform path lengths within each bank's local structure.
Solution Approach 2:
The patent distributes demultiplexer banks across both horizontal and vertical dimensions rather than concentrating them in a single vertical column. This two-dimensional distribution reduces the area occupied by any single demultiplexer structure while maintaining uniform signal path lengths through careful local arrangement within each bank.
3Reliability
If data signal lines have significantly different lengths, then charging rates vary causing striped unevenness in monochrome displays, but uniform arrangement increases device area
Solution Approach 1:
The demultiplexer is divided into multiple banks, each responsible for a specific group of data signal lines with controlled path lengths. This segmentation ensures that adjacent lines within each bank have similar lengths and charging rates, preventing striped unevenness while keeping each bank's area compact through localized arrangement.
Solution Approach 2:
The patent arranges demultiplexer banks in a two-dimensional grid pattern across the substrate rather than in a single linear array. This multi-dimensional distribution allows uniform path length control within each bank while reducing the total area required compared to a single extended vertical arrangement, thereby maintaining display uniformity with compact footprint.
Data Source
AI summary
A layout pattern of a demultiplexer circuit of a display device employing the SSD method is configured as described below. Specifically, demultiplexers in the demultiplexer circuit are grouped with three demultiplexers as one set, and nine transistors as switching elements included in the three demultiplexers of each set are arranged to be aligned in the extending direction of a source line with three transistors as a unit while positions of the nine transistors are sequentially shifted in the vertical direction with respect to the source line. Furthermore, any two adjacent sets are arranged such that a direction in which nine transistors included in one set are shifted in the vertical direction with three transistors as a unit and a direction in which nine transistors in the other set are shifted in the above-described vertical direction with three transistors as a unit are opposite to each other.