Demultiplexer Clock Division With Stable Phase Alignment
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Solution Overview
Problem
Existing frequency divider circuits face challenges in maintaining a desired phase relationship between frequency-divided clock signals, especially when input clock signals become unstable due to noise, leading to unpredictable phase relationships between output signals.
Innovation Solution
A frequency divider circuit comprising a first frequency dividing circuit, a second frequency dividing circuit, a detection circuit, and a selection circuit that detects the phase relationship between the frequency-divided clock signals and selects one of the signals or its inverted version to maintain a desired phase relationship, ensuring stability even under noisy conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional frequency divider circuit is used to divide clock signals, then the circuit structure is simple, but the phase relationship between frequency-divided clock signals becomes unpredictable when input clock signals are unstable due to noise
Solution Approach 1:
The patent introduces a feedback mechanism where the phase relationship between frequency-divided clock signals is continuously monitored. When phase deviation is detected, the system automatically adjusts the output phase by selecting between normal and inverted signals, creating a closed-loop control system that maintains stable phase relationships despite input instability
Solution Approach 2:
The patent implements dynamic phase adjustment by providing multiple output paths (normal and inverted signals) that can be selectively activated based on detected phase conditions. This dynamic switching capability allows the circuit to adapt to changing input conditions and maintain desired phase relationships
2Reliability
If control logic is added to maintain phase relationships during reset and operation, then phase stability improves, but the circuit becomes more complex and sensitive to noise-induced clock inversions
Solution Approach 1:
The patent changes the operational parameter by providing both normal and inverted frequency-divided clock signals as output options. This parameter variation allows the system to compensate for phase deviations caused by noise by selecting the appropriate signal polarity, thereby reducing the harmful effects of noise without requiring complex noise filtering circuits
3Productivity
If multiple frequency divider circuits are used to generate multiple frequency-divided clock signals, then the quantity of clock signals increases, but maintaining coincident phases between all signals becomes difficult
Solution Approach 1:
The patent creates a universal phase management approach where each frequency divider circuit is equipped with the same phase detection and adjustment capability. This allows multiple independent frequency divider circuits to maintain consistent phase relationships with each other, enabling the system to generate multiple coincident phase clock signals reliably
Data Source
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AI summary
A demultiplexer circuit comprises: a first demultiplexing circuit (105) configured to convert a first input signal (IDT 0,1) having a first bit width (2) into a first intermediate signal having a second bit width (4) larger than the first bit width, based on a first conversion clock signal (101out) generated by dividing a first clock signal (IDTclk); a second demultiplexing circuit (109) configured to convert a second input signal (IBD 0,1) having the first bit width (2) and having a first phase difference with respect to the first input signal into a second intermediate signal having the second bit width (4), based on a second conversion clock signal (104out) generated by dividing a second clock signal (IBDclk) having the same frequency as the first clock signal (IDTclk) and having the first phase difference with respect to the first clock signal; a first frequency divider circuit (102) configured to divide the first conversion clock signal to generate a third conversion clock signal (102out) having a lower frequency than the first conversion clock signal; a third demultiplexing circuit (106) configured to convert the first intermediate signal into a first output signal having a third bit width (8) larger than the second bit width (4), based on the third conversion clock signal (102out); and a fourth demultiplexing circuit (110) configured to convert the second intermediate signal into a second output signal having the third bit width (8), based on the third conversion clock signal (102out).