Demultiplexing Circuit With Threshold Voltage Compensation Reset
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Solution Overview
Problem
The positive drift of the threshold voltage in data writing transistors due to increased voltage and current pressure in demultiplexers leads to premature failure, reducing the lifespan of display devices.
Innovation Solution
A demultiplexing circuit with a switch control module and compensation units that detect and compensate for the threshold voltage of data writing transistors, using clock signals and compensation control signals to reset and stabilize the voltage levels, thereby extending the circuit's operating life.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the demultiplexer writes more signals in the same time, then the number of data driver chips is reduced and manufacturing cost is reduced, but the transistors are subject to greater pressure on voltage and current which accelerates aging and causes positive drift of threshold voltage
Solution Approach 1:
The patent applies preliminary action by resetting the voltage level of the control end of the data writing transistor before the threshold voltage drift occurs during normal operation. The switch control module outputs clock signals to reset transistors in advance, preventing the accumulation of voltage stress that would otherwise lead to threshold voltage positive drift and transistor failure.
Solution Approach 2:
The patent implements feedback through the compensation unit that continuously monitors the threshold voltage of the data writing transistor and provides compensation control signals. When threshold voltage drift is detected, the feedback mechanism activates the reset function to correct the voltage level, creating a closed-loop control system that maintains transistor reliability despite high-speed operation.
2Productivity
If the demultiplexer writes more signals in the same time, then the signal processing capacity is improved, but the operating life of the demultiplexer is reduced due to accelerated transistor aging
Solution Approach 1:
The patent applies periodic action through the clock signal that periodically resets the voltage level of the data writing transistor control end. This periodic resetting prevents continuous voltage stress accumulation during high-speed signal writing, allowing the demultiplexer to maintain high productivity while extending transistor operating life by cyclically refreshing the voltage states.
Solution Approach 2:
The patent implements beforehand cushioning by providing a protection function through the reset mechanism that cushions against voltage stress before it causes damage. The switch control module proactively resets transistors based on clock signals, preventing the cumulative voltage stress that would otherwise accelerate aging and reduce operating life during intensive signal processing.
3Device complexity
If the voltage level of the control end of the data writing transistor is not reset, then the circuit operation is simpler, but the threshold voltage drift causes signal writing errors and circuit failure
Solution Approach 1:
The patent introduces an intermediary element - the reset transistor controlled by the clock signal - that mediates between the simple circuit operation and the need for threshold voltage compensation. This intermediary periodically resets the control end voltage level, maintaining signal writing accuracy without requiring complex continuous monitoring and adjustment circuits.
Data Source
AI summary
The present application provides a demultiplexing circuit, a control method thereof and a display device, which include at least one demultiplexing module and a switch control module. A compensation unit of each demultiplexing unit in the demultiplexing module is coupled to a voltage level of an output end of a data writing transistor according to a clock signal received by a control end of the data writing transistor. The output end of each switch control unit of the switch control module is electrically connected to the control end of the data writing transistor included in a demultiplexing unit.