Demultiplexer Circuit Adjustable Parasitic Capacitance
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Solution Overview
Problem
Existing demultiplexers in display panels have fixed parasitic capacitances due to thin film transistors, leading to increased power consumption, which is detrimental to display devices.
Innovation Solution
A demultiplexer circuit with multiple switching transistor groups, where the sources and drains of each group are connected in common, allowing for adjustable channel width-to-length ratio and parasitic capacitance through control of driving signals, reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fixed-size thin film transistors are used in the demultiplexer, then the device structure is simple and easy to manufacture, but the parasitic capacitance is fixed and cannot be adjusted, leading to increased power consumption
Solution Approach 1:
The patent applies the dynamics principle by making the transistor channel width adjustable rather than fixed. The demultiplexer circuit includes multiple transistor groups (first transistor group, second transistor group, etc.) that can be selectively activated. By dynamically adjusting which transistor groups are active based on driving signals, the effective channel width changes, thereby adjusting the parasitic capacitance to match different driving conditions and reduce power consumption.
Solution Approach 2:
The patent applies parameter changes by modifying the effective channel width parameter of the transistors. Through selective activation of different transistor groups with different channel widths, the parasitic capacitance parameter is adjusted according to the driving signals. This allows the system to optimize power consumption by matching the transistor parameters to the specific operating conditions.
2Use of energy by moving object
If multiple transistor groups with adjustable channel width are used, then parasitic capacitance can be adjusted to reduce power consumption, but the device structure becomes more complex
Solution Approach 1:
The patent applies segmentation by dividing the transistor structure into multiple independent transistor groups (first transistor group, second transistor group, third transistor group, etc.), where each group has a different channel width. These segmented groups can be selectively activated based on driving signals, allowing adjustment of the effective parasitic capacitance without requiring a completely redesign of the entire transistor structure.
Solution Approach 2:
The patent applies merging by combining multiple transistor groups with different channel widths into a single integrated demultiplexer structure. The source and drain regions are shared among the transistor groups, and the gate electrodes are controlled by different control signals. This merging approach allows the system to achieve adjustable parasitic capacitance while maintaining a relatively compact and integrated device structure.
Data Source
AI summary
Provided are a demultiplexer circuit, an array substrate, a display panel and device, and a driving method. The demultiplexer circuit includes multiple demultiplexers, each demultiplexer includes at least two switching transistor groups, and each switching transistor group includes at least two switching transistors. Sources of the at least two switching transistors in a same switching transistor group are electrically connected to each other, drains of the at least two switching transistors in the same switching transistor group are electrically connected to each other. Input ends of the at least two switching transistor groups in a same demultiplexer are electrically connected to each other. In the same switching transistor group, the common source is electrically connected to the input end, the common drain is electrically connected to the output end, and at least two control ends are electrically connected to gates of the switching transistors in a one-to-one correspondence.