Demultiplexer Circuit Pin Reduction Logic
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Solution Overview
Problem
High-resolution thin-film-transistor liquid crystal displays face challenges due to the high number of output pins required for demultiplexer circuits, increasing the cost and complexity of integrated circuits.
Innovation Solution
A circuit is designed with a logic unit that transforms three pulse signals into four or eight control signals, reducing the need for individual pins on the integrated circuit by using NAND gates and buffers to generate the necessary control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional demultiplexer circuits use individual pins for each timing control signal, then the control signals can be output reliably, but the number of output pins increases significantly
Solution Approach 1:
The patent merges multiple timing control signals (CKR, CKG, CKB, CKW) into a single composite control signal line. By combining these signals that were previously transmitted separately through individual pins, the circuit reduces the number of required output pins while maintaining the ability to deliver all necessary control functions to the demultiplexer circuit.
Solution Approach 2:
The single control signal line is designed to serve multiple functions simultaneously, carrying timing information for multiple control signals (CKR, CKG, CKB, CKW) through encoding or multiplexing techniques. This multi-functional approach allows one pin to replace what would traditionally require four separate pins, reducing device complexity while preserving reliability.
2Manufacturing precision
If more output pins are used for control signals, then the demultiplexer can be controlled accurately, but the product cost increases
Solution Approach 1:
By merging multiple control signal lines into a single composite signal line, the patent reduces the number of required IC output pins. This reduction directly lowers manufacturing costs associated with pin fabrication, packaging, and assembly, while the signal encoding ensures that demultiplexer control accuracy is maintained through proper signal reconstruction at the receiving end.
Solution Approach 2:
The patent changes the parameter of signal transmission by encoding multiple control signals into a single composite signal with specific timing characteristics. This parameter transformation allows the system to convey the same control information using fewer physical channels, thereby reducing production costs while maintaining control precision through the structured signal format.
3Reliability
If four or eight timing control signals are output separately, then the demultiplexer functions correctly, but the integrated circuit requires more pins
Solution Approach 1:
The patent employs periodic action by transmitting multiple control signals in a time-division multiplexed manner through a single pin. The composite control signal contains sequentially arranged timing information for CKR, CKG, CKB, and CKW, allowing the demultiplexer to correctly reconstruct and identify each control signal through timing detection, thereby maintaining functional correctness while reducing pin count.
Solution Approach 2:
The patent transitions from a spatial dimension approach (multiple parallel signal lines) to a temporal dimension approach (single signal line with time-division multiplexing). By encoding multiple control signals in the time domain rather than requiring separate spatial channels, the circuit reduces the number of integrated circuit pins needed while ensuring correct demultiplexer operation through timing-based signal identification.
Data Source
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AI summary
Provided are a liquid crystal display and a demultiplexer circuit thereof. The demultiplexer circuit comprises an integrated circuit unit (11) and a logic unit (12) electrically connected to the integrated circuit unit (11). The integrated circuit unit (11) outputs three pulse signals, namely a first pulse signal (V1), a second pulse signal (V2) and a third pulse signal (V3). The logic unit (12) converts the three pulse signals (V1-V3) in different electric level states to at least four control signals (CKR, CKG, CKB, CKW).