Demultiplexer Defect Detection via DC Voltage Switching
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Solution Overview
Problem
Existing methods for detecting defects in demultiplexers and lines within display devices, such as those in active matrix display panels, fail to effectively identify issues between the demultiplexer and the data driving circuit, particularly with thin film transistors, during the process of checking for mura, black/white spots, and line defects.
Innovation Solution
A defect detecting device and method that utilizes a demultiplexer with first and second TFTs connected to data lines, employing DC voltages and gate signals to differentiate between normal and shorted lines by controlling the state of switches and TFTs to determine defects based on light emission characteristics of pixel arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the demultiplexer is kept in off state during checking operation, then the checking process is simple, but defects in lines and TFTs of the demultiplexer cannot be detected
Solution Approach 1:
The patent applies preliminary action by turning on specific TFTs (first or second TFTs) before the checking operation to establish a test configuration. This allows the checking process to detect defects in lines and TFTs by creating a specific electrical path through the demultiplexer, while keeping the overall checking流程 relatively simple.
2Measurement precision
If DC voltage is applied to detect line defects, then line short defects can be detected, but the demultiplexer TFTs remain undetected when in off state
Solution Approach 1:
The patent applies dynamics by dynamically controlling the state of TFTs (turning them on or off) during the checking operation. By turning on specific TFTs before applying DC voltage, the system creates different electrical paths that enable detection of both line defects and demultiplexer TFT defects, making the detection system adaptive rather than static.
Solution Approach 2:
The patent changes the electrical state parameter of the TFTs from off to on during the checking process. This parameter change enables the detection of defects in both lines and demultiplexer TFTs by creating a conductive path through the demultiplexer, allowing DC voltage to reach and test the TFTs that would otherwise remain inactive.
3Productivity
If all TFTs in the demultiplexer are turned on simultaneously, then all lines can be tested, but it becomes impossible to distinguish which specific TFT is defective
Solution Approach 1:
The patent applies segmentation by dividing the TFTs in the demultiplexer into separate groups (first TFTs and second TFTs) that are controlled independently. By turning on only one group at a time while keeping the other group off, the system can test all lines through different paths and identify which specific TFT is defective based on which group was active during the defect detection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables accurate detection of defects in demultiplexers and lines by distinguishing between normal and shorted conditions through controlled DC voltage application and gate signal management, improving the ability to identify and diagnose issues in display panel components.
Implementation Method 1
The red, green, and blue pixels emit light by the R DC voltage, the G DC voltage, and the B DC voltage
Data Source
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AI summary
Embodiments relate to a defect detecting method of a line (L1) and a demultiplexer (200), a defect detecting device (100), and a display panel including the defect detecting device (100). A demultiplexer (200) may connect a plurality of data lines (D1, D2, ..., Dm) to a plurality of corresponding lines (L1, L2,..., Lk). The defect detecting device includes DC lines (DC_R, DC_G, DC_B) supplied with respective DC voltages, first switches (T11, T12, ..., T1a) connected to the DC lines (DC_R, DC_G, DC_B) and configured to transmit the respective DC voltages to the corresponding first data lines (D1, D2, D3, D7, D8, D9) among a plurality of data lines (D1, D2, ..., Dm) according to a first gate signal, and second switches (T21, T22,..., T2b) connected to the first to third DC lines (DC_R, DC_G, DC_B) and configured to transmit one of the respective DC voltages to corresponding second data lines (D4, D5, D6, Dm-5, Dm-4, Dm-3) among a plurality of data lines (D1, D2, ..., Dm) according to a second gate signal.