Demultiplexer Circuit for Display Data Line Management

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Solution Overview

Problem

As display panel sizes increase, the number of data lines grows, exceeding the driving capacity of integrated circuits (ICs), necessitating more data driver ICs, which can lead to image quality deterioration.

Innovation Solution

A display device configuration that includes a demultiplexer circuit with transistors and capacitors to manage data signals across multiple data lines using selection signals, reducing the number of data driver ICs required while maintaining image quality by compensating for kick-back voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the number of data lines is increased to support larger display panels, then the display size is improved, but the number of data driver ICs required increases

Engineering Contradiction:
Improvedisplay sizeVSAvoidnumber of data driver ICs
Core Design Contradiction:
Volume of moving objectVSDevice complexity

Solution Approach 1:

The data lines are divided into multiple groups, with each group controlled by a separate data driver IC. A demultiplexer circuit routes data signals from fewer driver ICs to multiple data line groups, enabling one IC to control multiple segments of data lines through time-multiplexed signal distribution

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A demultiplexer circuit is introduced as an intermediary component between the data driver ICs and the data lines. This mediator receives data signals from driver ICs and distributes them to appropriate data line groups based on selection signals, reducing the direct one-to-one connection requirement

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If the number of data driver ICs is reduced, then the device complexity is improved, but the image quality deteriorates due to kick-back voltage

Engineering Contradiction:
Improvenumber of data driver ICsVSAvoidimage quality
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

Capacitors are connected to data lines that are not currently being driven to preemptively counteract the kick-back voltage effect. When a data line group is not active, its associated capacitor maintains the voltage level, preventing the voltage drop that would otherwise occur due to parasitic capacitance discharge

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The system uses selection signals to coordinate the timing of data signal distribution and capacitor charging/discharging cycles. The demultiplexer monitors which data line groups are active and adjusts capacitor behavior accordingly, creating a feedback mechanism that maintains voltage stability across all data lines

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces the number of data driver ICs needed by half and prevents image quality deterioration by accurately managing data signal distribution and kick-back voltage compensation.

Implementation Method 1

a first capacitor connected between the second selection signal and the first data line

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS9741306B2Display device
Publication Date: 2017.08.22 SAMSUNG DISPLAY CO LTD
  • US9741306B2 patent drawing
  • US9741306B2 patent drawing
  • US9741306B2 patent drawing

AI summary

According to an embodiment, a display device includes a display panel including a plurality of pixels respectively connected to a plurality of gate lines and a plurality of data lines, a gate driver driving the plurality of gate lines, a data driver configured to output a plurality of data output signals to the plurality of data lines in response to a data signal, a demultiplexer circuit configured to provide the plurality of data output signals to the plurality of data lines in response to a first selection signal and a second selection signal; and a timing controller configured to provide the data signal to the data driver, outputting the first selection signal and the second selection signal, and controlling the gate driver.