Demultiplex Display Driving Circuit for RGBW Sub-Pixel Charging
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Solution Overview
Problem
High-resolution display devices face challenges in ensuring sufficient charging time and rate of data signals due to shortened pulse durations of scan signals, leading to inadequate voltage levels in sub-pixels.
Innovation Solution
A demultiplex type display driving circuit with 24 data lines and 48 sub-pixels, each coupled to a scan line and data line, utilizing eight demultiplex modules with three thin film transistors each, where the pulse duration of branch control signals is increased to ⅓ of the scan signal duration, allowing for improved data signal charging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of the display device is increased, then the display quality is improved, but the pulse duration of the scan signal is shortened, leading to insufficient charging time for sub-pixels
Solution Approach 1:
The patent divides the data signal transmission into multiple time segments using demultiplex modules. Each module handles a subset of data lines with extended control signal duration, allowing the data signal to be transmitted in phases rather than simultaneously across all lines, thus extending the effective charging time for each sub-pixel group.
Solution Approach 2:
The demultiplex modules receive and process data signals in advance before the actual display scanning occurs. By pre-charging the data lines through extended control signal duration, the system ensures that sufficient voltage levels are established before the sub-pixels need to be activated, compensating for the shortened overall scan signal duration.
2Productivity
If the pulse duration of scan signal is shortened to accommodate high resolution, then more data lines can be driven, but the charging rate of sub-pixels becomes insufficient
Solution Approach 1:
The patent segments the data line driving task into multiple demultiplex modules, where each module is responsible for a specific subset of data lines. This segmentation allows each module to dedicate sufficient time to charge its assigned data lines fully, maintaining high charging rates while collectively driving a larger number of data lines across all modules.
Solution Approach 2:
The system dynamically adjusts the control signal duration for each demultiplex module to be longer than the overall scan signal duration. This dynamic timing adjustment ensures that each module has adequate time to charge its data lines at the required rate, even though the total scan time is compressed for high-resolution display.
Data Source
AI summary
Disclosed is a demultiplex type display driving circuit, applied in a RGBW four colors pixel structure display device, comprising a plurality of driving units, and each driving unit comprises eight demultiplex modules, and each demultiplex module comprises three thin film transistors, and gates of the three thin film transistors are electrically coupled to a first branch control signal (Demux1), a second branch control signal (Demux2), and a third branch control signal (Demux3) respectively, and source are electrically coupled to the same data signal, and drains are electrically coupled to one data line in a jump manner, respectively. Thus, the pulse duration of each branch control signal is equal to ⅓ of a pulse duration of the scan signal to increase the charging time of the data signal and promote the charging rate of the sub pixel under circumstance that the pulse duration of the scan signal is not changed.