Demultiplexer Segments I2C Bus for Multiple Slave Devices
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Solution Overview
Problem
Existing communication protocols face challenges in addressing multiple slave devices with the same address over a single bus system, leading to bus loading and limitations in signal strength and power consumption.
Innovation Solution
A multi-bus configuration using a bus master with a de-multiplexer to selectively communicate with multiple I2C slave devices over separate data and clock busses, allowing for independent addressing and reduced signal resistor strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple slave devices with the same address are connected to a single bus system, then the ability to communicate with multiple devices is improved, but bus loading increases and signal strength deteriorates
Solution Approach 1:
The patent divides a single I2C bus into multiple separate data busses (first data bus, second data bus, etc.) that share a common clock bus. This segmentation allows slave devices with the same address to be connected to different data busses without interfering with each other's signal integrity, as each data bus operates independently while synchronized by the shared clock.
Solution Approach 2:
The patent introduces a de-multiplexer as an intermediary component that receives data from the master device and selectively routes it to the appropriate data bus based on a select signal. This mediator enables the master to communicate with multiple slave devices on different busses while maintaining proper signal distribution and timing.
2Adaptability or versatility
If multiple slave devices share the same address on a single bus, then device addressing flexibility is improved, but power consumption increases
Solution Approach 1:
By segmenting the single data bus into multiple separate data busses, the patent enables multiple slave devices with identical addresses to operate simultaneously on different busses. This eliminates the need for devices to contend for bus access, reducing the power consumption associated with bus arbitration and repeated transmission attempts.
Solution Approach 2:
The patent uses a shared clock bus that provides periodic clock signals to synchronize data transmission across multiple data busses. This periodic action allows the master device to systematically select and communicate with different slave devices on different busses in a structured manner, improving power efficiency compared to uncoordinated single-bus access.
3Device complexity
If a single bus system is used to connect multiple slave devices, then system complexity is reduced, but bus loading increases
Solution Approach 1:
The patent segments the data transmission path into multiple parallel data busses while maintaining a single shared clock bus. This segmentation distributes the data traffic load across multiple channels, reducing congestion on individual busses while keeping the overall system architecture relatively simple through the shared clock infrastructure.
Solution Approach 2:
The patent adds a dimensional aspect to the bus system by creating multiple data busses that operate in parallel, distinguished by select signal states. This dimensional expansion allows the system to handle increased bus loading by distributing traffic across multiple channels while maintaining manageable complexity through the shared clock synchronization mechanism.
Data Source
AI summary
A device comprising: a bus master, including a bi-directional data and clock lines, configured to produce a select signal output for enabling data transmission on the bi-directional data line to first/second different data busses supporting multiple slave devices configured to receive/transmit data over a respective data bus and to receive a clock signal from the bus master from the clock line; and a de-multiplexer including an input, first and second outputs and a control input, the input coupled to the bi-directional data line of the bus master, first/second outputs of the de-multiplexer coupled to first/second data busses, respectively, and the control input configured to receive the select signal from the bus master that is configured to communicate to a first slave device when the select signal is in a first state, and a second different slave device when the select signal is in a second different state.