Demultiplexer Pre-Charge Circuit for Narrow Bezel Displays

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Solution Overview

Problem

The implementation of a narrow bezel in display devices is limited by the size of transistors in demultiplexers, which are used to output data signals to a larger number of data lines than output lines, hindering low power consumption and bezel reduction.

Innovation Solution

A demultiplexer design incorporating first and second transistors connected between data input and output terminals, with pre-charge circuits including transistors, diodes, and capacitors, allowing for efficient time-divisional output of data signals and reducing transistor size through enhanced clock signal management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a demultiplexer is added to output lines of the data driver to time-divisionally output data signals to more data lines than output lines, then the number of data lines can be larger than output lines, but the transistor size limits implementation of narrow bezel

Engineering Contradiction:
Improvenumber of data linesVSAvoidbezel width
Core Design Contradiction:
Quantity of substanceVSLength of moving object

Solution Approach 1:

The demultiplexer divides the data signal transmission into multiple time-divisional channels using multiple transistors (first transistor for first data line, second transistor for second data line), allowing one output line to serve multiple data lines through time-divisional multiplexing. This segmentation enables the number of data lines to exceed the number of physical output lines while reducing the required transistor size for each individual switch.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The pre-charge circuits charge the gate electrodes of the first and second transistors in advance during non-active periods. The first pre-charge circuit charges the gate electrode of the first transistor when it is not selected, and the second pre-charge circuit charges the gate electrode of the second transistor when it is not selected. This preliminary charging reduces the required voltage swing during switching, enabling smaller transistor sizes and narrower bezels.

Inventive Principle:
Principle #10Preliminary action

2Length of moving object

If transistor size is reduced to achieve narrow bezel, then bezel width decreases, but transistor driving speed may be insufficient for efficient data signal output

Engineering Contradiction:
Improvebezel widthVSAvoidtransistor driving speed
Core Design Contradiction:
Length of moving objectVSSpeed

Solution Approach 1:

The pre-charge circuits perform preliminary charging of the gate electrodes before the transistors need to switch. By charging the gate electrodes in advance during periods when the transistors are not actively switching data signals, the circuits prepare the transistors for rapid switching without requiring large voltage swings during the actual data transmission, thus maintaining high driving speed with smaller transistor sizes.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The demultiplexer operates in periodic time-divisional cycles where the first transistor and second transistor are alternately activated. During each cycle, one transistor is actively switching data signals while the other is being pre-charged or is non-conductive. This periodic operation pattern allows small transistors to achieve sufficient driving speed by optimizing their switching timing and utilizing the pre-charge periods for recovery and preparation.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS9852674B2Demultiplexer and display device including the same
Publication Date: 2017.12.26 SAMSUNG DISPLAY CO LTD
  • US9852674B2 patent drawing
  • US9852674B2 patent drawing
  • US9852674B2 patent drawing

AI summary

A demultiplexer includes: a first transistor connected between a data input terminal and a first output terminal; a second transistor connected between the data input terminal and a second output terminal; and a first pre-charge circuit connected to a gate electrode of the first transistor, the first pre-charge circuit including: a third transistor and a first diode connected between a first clock input terminal and the gate electrode of the first transistor in parallel; and a first capacitor connected between a second clock input terminal and the gate electrode of the first transistor.