Demultiplexer Wiring Space Reduction for High-Resolution Displays
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Solution Overview
Problem
Existing display technologies face challenges in completing the wiring of demultiplexers, data lines, and their leads on high-resolution display panels with narrow bezels and small or medium sizes.
Innovation Solution
The proposed solution involves an array substrate with a demultiplexer that includes thin film transistors and control gate lines arranged in a specific configuration to save wiring space. The demultiplexer is designed with the first to third thin film transistors on one side and the fourth to sixth thin film transistors on the opposite side, with data line leads and data lines positioned on opposite sides of the control gate lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the demultiplexer, data lines and their leads are wired on a display panel with high resolution and small or medium size, then the display quality is improved, but the wiring space becomes insufficient
Solution Approach 1:
The patent applies dimensionality change by routing data line leads and data lines on opposite sides of control gate lines, transitioning from a planar arrangement to a three-dimensional spatial configuration. This allows wiring to utilize vertical space above and below the gate lines, effectively doubling the available wiring area without increasing the panel's footprint, thereby resolving the contradiction between limited wiring space and high display quality requirements.
Solution Approach 2:
The patent segments the wiring arrangement by dividing data line leads and data lines into two separate groups positioned on opposite sides of the control gate lines. This segmentation prevents wiring congestion by distributing signal paths across different spatial zones, allowing independent routing optimization for each group and enabling complete wiring coverage on high-resolution panels with narrow bezels.
2Measurement precision
If the demultiplexer is configured with more transistors and wiring to support high resolution displays, then the display quality is improved, but the device complexity increases
Solution Approach 1:
The patent employs asymmetric configuration by positioning the first to third thin film transistors on one side of the demultiplexer and the fourth to sixth thin film transistors on the opposite side. This asymmetric layout optimizes signal routing paths, reduces cross-interference between adjacent wiring, and simplifies the overall wiring complexity while maintaining the functionality required for high-resolution display quality.
3Measurement precision
If the wiring density is increased to accommodate high resolution displays with narrow bezels, then the display quality is improved, but the manufacturing precision requirements become more stringent
Solution Approach 1:
By utilizing the third dimension (vertical spacing above and below control gate lines) for wiring arrangement, the patent reduces wiring density in the planar direction. This dimensional transition lowers the stringency of manufacturing precision requirements for wiring fabrication while still achieving the wiring capacity needed for high-resolution displays with narrow bezels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the wiring space required for demultiplexers, data lines, and data line leads on display panels, facilitating the completion of wiring on panels with medium or small sizes while maintaining improved display quality.
Implementation Method 1
a liquid crystal composition comprising a first liquid crystal compound and a second liquid crystal compound
Data Source
Figure 1
Figure 2
Figure 3a~3b
AI summary
The present disclosure provides a demultiplexer, an array substrate and a display device. The array substrate comprises a plurality of data line leads, a plurality of data lines arranged side by side and the demultiplexer. The demultiplexer includes first to third control gate lines arranged in parallel and first to sixth thin film transistors. The first thin film transistor to the third thin film transistor are positioned at a side of the demultiplexer proximal to the first control gate line, the fourth thin film transistor to the sixth thin film transistor are positioned at a side of the demultiplexer proximal to the third control gate line, and drains of the first thin film transistor to the sixth thin film transistor are respectively coupled to corresponding ones of the plurality of data lines.