Denoising Neural Network for High Density Memory Noise
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Solution Overview
Problem
The increasing demand for parameters in neural networks leads to challenges in computational resources, energy consumption, and model interpretability, with a significant bottleneck in memory-processor communication in artificial intelligence accelerators.
Innovation Solution
The integration of high-density memories with denoising neural networks, which can be formed on the same substrate as processors, to reduce the impact of noise and allow for more dense, lower power, and faster memory designs while maintaining storage fidelity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-density memory is designed with multi-value storage elements to increase storage capacity, then memory density is improved, but noise from defects, cross talk, and read/write operations increases
Solution Approach 1:
A neural network is introduced as an intermediary component between the memory array and the external system. The neural network receives noisy read values from the high-density memory, processes them through learned denoising transformations, and outputs cleaned values. This intermediary structure enables the system to tolerate and correct the noise inherent in high-density multi-value storage without sacrificing storage capacity.
2Quantity of substance
If memory density is increased to meet growing parameter demands, then storage capacity is improved, but communication bottleneck with processor worsens
Solution Approach 1:
The neural network acts as an on-chip intermediary that processes memory data before it needs to be communicated with external processors. By performing denoising operations locally within the memory device, the system reduces the amount of data that needs to be transferred and processed externally, thereby alleviating the communication bottleneck while maintaining high storage capacity.
Data Source
AI summary
Methods and systems which involve computer memories are disclosed herein. A memory in accordance with this disclosure can be a multi-value memory in which each storage element of the memory can store multiple values as opposed to a standard binary storage element. The memory can include a decoder neural network and an encoder neural network to denoise the values in the memory. Various approaches disclosed herein overcome design constraints that would otherwise limit the density of such a memory.