Dense Redistribution Layers for Small-Via Semiconductor Packaging
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and efficient packaging of semiconductor dies, particularly in Package-on-Package (PoP) technology, where smaller and more creative packaging techniques are needed to enhance functionality and reduce footprint.
Innovation Solution
The development of dense redistribution layers (RDLs) in semiconductor packages, utilizing high-resolution photoresists to define conductive vias and metallization patterns, which include the formation of conductive lines and vias in redistribution layers, improving planarity and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional packaging techniques are used, then manufacturing simplicity is maintained, but integration density and functionality are limited
Solution Approach 1:
The patent implements Package-on-Package (PoP) technology where a top semiconductor package is stacked on top of a bottom semiconductor package, creating a nested three-dimensional structure that increases integration density without increasing footprint area
Solution Approach 2:
The invention transitions from two-dimensional planar packaging to three-dimensional vertical stacking by adding redistribution layers that route signals in multiple layers, enabling higher component density through vertical integration
2Quantity of substance
If feature size is reduced to increase integration density, then more components can be integrated, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the interconnect structure into multiple segments including conductive vias, redistribution layers, and dielectric layers, allowing each segment to be optimized and manufactured separately with appropriate precision requirements
Solution Approach 2:
The invention changes the dimensional parameters of conductive vias and redistribution layer features to achieve higher density while maintaining manufacturability through optimized via diameter, spacing, and layer thickness parameters
3Quantity of substance
If conductive vias are made smaller to increase density, then integration is improved, but via formation difficulty increases
Solution Approach 1:
The patent forms a seed layer on the conductive via surfaces before plating, preparing the surface in advance to facilitate controlled metal deposition and simplify the via formation process for small features
Solution Approach 2:
The invention introduces a seed layer as an intermediary between the dielectric material and the final conductive material, enabling controlled plating of small via features and simplifying the overall manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for smaller conductive vias, enhances manufacturing efficiency, and improves planarity in redistribution layers, leading to more compact and functional semiconductor devices.
Implementation Method 1
utilizing high-resolution photoresists to define conductive vias and metallization patterns
Implementation Method 2
plating a first conductive material in the first opening on the seed layer
Data Source
AI summary
A method embodiment includes forming a patterned first photo resist over a seed layer. A first opening in the patterned first photo resist exposes the seed layer. The method further includes plating a first conductive material in the first opening on the seed layer, removing the patterned first photo resist, and after removing the patterned first photo resist, forming a patterned second photo resist over the first conductive material. A second opening in the patterned second photo resist exposes a portion of the first conductive material. The method further includes plating a second conductive material in the second opening on the first conductive material, removing the patterned second photo resist, and after removing the patterned second photo resist, depositing a dielectric layer around the first conductive material and the second conductive material.