Dense Redistribution Layers With Smaller Conductive Vias
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving higher integration density and smaller packaging techniques for semiconductor dies, particularly in Package-on-Package (PoP) devices, where traditional methods struggle with manufacturing costs and resolution issues in forming conductive features in redistribution layers.
Innovation Solution
The development of high-resolution photoresist materials and processes for forming conductive vias and metallization patterns in redistribution layers, allowing for smaller conductive features and improved planarity, which are applied in semiconductor package fabrication, including the use of polymers like polybenzoxazole (PBO) and silicon nitride, and techniques such as spin coating and chemical vapor deposition (CVD) to create dielectric and metallization layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photoresist materials and processes are used for forming conductive features in redistribution layers, then manufacturing processes are simpler and more established, but resolution is insufficient to create smaller conductive features
Solution Approach 1:
The patent changes the chemical and physical parameters of the photoresist material itself by using a two-tone photoresist composition with distinct exposed and unexposed regions. This material parameter change enables higher resolution patterning (smaller conductive features) while maintaining ease of manufacture through a modified but still relatively simple dual-tone lithography process.
Solution Approach 2:
The patent replaces traditional single-tone photoresist patterning mechanics with a two-tone photoresist system that uses differential etching rates. This substitution allows for more precise control of conductive feature dimensions and spacing, achieving smaller features while keeping the manufacturing process accessible through standard lithography equipment.
2Productivity
If conductive via size is reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the photoresist material parameters by utilizing two-tone photoresist with different etching rates for exposed and unexposed regions. This enables precise control of conductive via dimensions at smaller sizes, allowing higher integration density without sacrificing manufacturing precision. The differential etching provides self-aligned features that maintain dimensional control even at reduced via sizes.
3Adaptability or versatility
If redistribution layers are made more complex to enhance functionality, then device capabilities improve, but planarity control becomes more difficult
Solution Approach 1:
The patent segments the photoresist layer into two distinct functional regions with different properties: an exposed region and an unexposed region. This segmentation allows the redistribution layer to have complex patterns while maintaining planarity, as each segment can be independently controlled during the dual-tone lithography process. The segmented approach enables enhanced device functionality through complex routing while preserving manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables smaller conductive vias, reduces manufacturing costs, and improves planarity in redistribution layers, enhancing the integration density and functionality of semiconductor devices while maintaining a small footprint.
Implementation Method 1
depositing a photoresist material over the encapsulant and the integrated circuit die, patterning a first opening in the photoresist material to expose a first conductive material, and plating a conductive via in the first opening
Implementation Method 2
depositing a photoresist material over the encapsulant and the integrated circuit die
Implementation Method 3
techniques such as spin coating and chemical vapor deposition (CVD) to create dielectric and metallization layers
Data Source
AI summary
A method embodiment includes forming a patterned first photo resist over a seed layer. A first opening in the patterned first photo resist exposes the seed layer. The method further includes plating a first conductive material in the first opening on the seed layer, removing the patterned first photo resist, and after removing the patterned first photo resist, forming a patterned second photo resist over the first conductive material. A second opening in the patterned second photo resist exposes a portion of the first conductive material. The method further includes plating a second conductive material in the second opening on the first conductive material, removing the patterned second photo resist, and after removing the patterned second photo resist, depositing a dielectric layer around the first conductive material and the second conductive material.