Fin Sidewall Spacers for Dense Source/Drain Epitaxy Isolation
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Solution Overview
Problem
Aggressive scaling down of semiconductor integrated circuit (IC) dimensions leads to densely spaced active regions, causing source/drain features to merge, resulting in electrical issues and increased parasitic capacitance due to dielectric fins, which degrades device performance.
Innovation Solution
The formation of fin sidewall (FSW) spacers during the epitaxial growth of source/drain features to prevent merging and provide sufficient volume, involving a method that includes forming a trench, depositing a sacrificial structure, conformally depositing a dielectric film, etching to form FSW spacers, and removing the sacrificial structure to confine epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If source/drain features are formed in densely spaced active regions to increase functional density, then production efficiency is improved, but the source/drain features may merge leading to electrical issues
Solution Approach 1:
The patent introduces dielectric fins that segment and isolate adjacent source/drain features physically, preventing their merger while allowing dense spacing of active regions. This segmentation maintains both high functional density and electrical isolation between features
Solution Approach 2:
Dielectric fins act as intermediary structures positioned between adjacent source/drain features. These fins provide the necessary electrical isolation and prevent merging, serving as a mediator that enables dense packing without compromising electrical performance
2Reliability
If dielectric fins are implemented to isolate adjacent source/drain features, then merging is prevented, but parasitic capacitance increases leading to degraded device performance
Solution Approach 1:
The patent modifies the physical parameters of the isolation structure by using thin dielectric fins with controlled thickness and material composition. By changing these parameters, the fins provide effective electrical isolation while minimizing the capacitance formed between adjacent source/drain features and the fins
Solution Approach 2:
The dielectric fins are formed using composite material structures with specific dielectric properties. The selection of dielectric materials with appropriate constants and the composite construction of fins allow optimization of both isolation effectiveness and parasitic capacitance characteristics
3Reliability
If source/drain features are formed with sufficient volume to provide adequate current conduction, then electrical performance is improved, but adjacent features may merge due to aggressive scaling
Solution Approach 1:
Dielectric fins segment the space between adjacent source/drain features, allowing each feature to achieve sufficient volume for current conduction while the fins maintain precise spacing control to prevent merging during fabrication
Solution Approach 2:
The dielectric fins are formed in advance before final source/drain feature completion. This preliminary action establishes the spacing boundaries early in the process, guiding subsequent fabrication steps and ensuring both adequate feature volume and precise spacing control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents the merging of adjacent source/drain features while maintaining satisfactory volumes, reducing parasitic capacitance and improving device performance by confining epitaxial growth with FSW spacers.
Implementation Method 1
conformally depositing a dielectric film over the workpiece
Implementation Method 2
forming an epitaxial source/drain feature in the source/drain trench
Data Source
AI summary
A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a substrate, an active region protruding from the substrate, and a dummy gate structure disposed over a channel region of the active region. The method also includes forming a trench in a source/drain region of the active region, forming a sacrificial structure in the trench, conformally depositing a dielectric film over the workpiece, performing a first etching process to etch back the dielectric film to form fin sidewall (FSW) spacers extending along sidewalls of the sacrificial structure, performing a second etching process to remove the sacrificial structure to expose the trench, forming an epitaxial source/drain feature in the trench such that a portion of the epitaxial source/drain feature being sandwiched by the FSW spacers, and replacing the dummy gate structure with a gate stack.