Density-Controlled Floorplan Design for Integrated Circuits
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Solution Overview
Problem
Increasingly dense integrated circuits (ICs) pose design challenges for electronic design automation (EDA) tools due to uncontrolled variations in pattern density, affecting the electrical performance of sensitive blocks and requiring innovative methods to manage pattern density effectively.
Innovation Solution
A method of density-controlled floorplan design that applies pattern density rules to limit and manage the pattern density around sensitive blocks by using decoupling capacitor (DCAP) cells, while reconfiguring insensitive blocks to maintain specified electrical performance metrics and reduce chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If IC density is increased to improve functionality, then the number of blocks and circuits increases, but pattern density variations become uncontrolled and electrical performance deteriorates
Solution Approach 1:
The patent applies different pattern density requirements to different blocks based on their electrical sensitivity. Pattern density sensitive blocks are surrounded by DCAP cells with specific density rules, while pattern density insensitive blocks have different density requirements. This local differentiation allows high IC density while maintaining electrical performance of sensitive blocks.
Solution Approach 2:
DCAP (decoupling capacitor) cells are introduced as intermediary elements between pattern density sensitive blocks. These DCAP cells act as buffers that control pattern density variations and prevent harmful density changes from affecting sensitive blocks, enabling higher overall IC density while protecting electrical performance.
2Reliability
If pattern density rules are applied to control density around sensitive blocks, then electrical performance is maintained, but chip area increases due to additional DCAP cells
Solution Approach 1:
The patent dynamically adjusts pattern density parameters for different blocks and regions. By changing density requirements based on block sensitivity and position, the design achieves electrical performance control without uniformly increasing chip area. The density rules are optimized to minimize area overhead while maintaining performance.
Solution Approach 2:
Pattern density rules and DCAP cells are applied selectively only to pattern density sensitive blocks and their surrounding regions, rather than uniformly across the entire chip. This partial application minimizes the area overhead while still protecting the electrical performance of sensitive blocks that require it.
3Reliability
If DCAP cells are added around sensitive blocks to control pattern density, then performance is improved, but device complexity increases
Solution Approach 1:
The patent segments blocks into pattern density sensitive and insensitive categories, and applies different design rules to each segment. This segmentation allows the floorplan design tool to handle complexity systematically by treating different block types differently, rather than applying uniform complex rules to all blocks.
Solution Approach 2:
The floorplan design tool automatically identifies pattern density sensitive blocks and applies appropriate DCAP cell placement and density rules without requiring manual intervention. The system serves itself by autonomously managing the complexity of density control, reducing the burden on designers while maintaining performance.
Data Source
AI summary
A method of density-controlled floorplan design for integrated circuits having a plurality of blocks includes positioning decoupling capacitor (DCAP) cells at least partially around a pattern density sensitive block. The method also includes changing at least a portion of a pattern density insensitive block adjacent to the pattern density sensitive block according to at least one pattern density rule.