Dependence-Based Replay Suppression in Processor Pipelines

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Solution Overview

Problem

In processors, speculative instruction execution leads to inefficiencies and increased power consumption due to the need for replaying mis-speculated instructions, particularly when store-to-load forwarding failures occur, causing dependent instructions to be unnecessarily awakened and executed.

Innovation Solution

Implementing a prediction mechanism to suppress the awakening of dependent instructions by tracking store-to-load dependencies, allowing store-to-load forwarding to occur before or concurrent with store data movement, and linking load instructions to their associated store instructions to prevent unnecessary replay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If speculative instruction execution is employed to enhance processing efficiency, then processor throughput is improved, but the number of instructions requiring replay increases and power consumption rises

Engineering Contradiction:
Improveprocessor throughputVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent applies preliminary action by predicting store-to-load dependencies before the load instruction executes. The dependency predictor proactively identifies potential dependencies between store instructions and subsequent load instructions, allowing the system to prepare for possible replay scenarios in advance. This enables the selective suppression of dependent instructions that would otherwise be unnecessarily awakened and executed, thereby reducing power consumption while maintaining speculative execution benefits.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If speculative instruction execution is employed to enhance processing efficiency, then processor throughput is improved, but the number of instructions subject to replay increases

Engineering Contradiction:
Improveprocessor throughputVSAvoidreplay overhead
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements feedback through the dependency predictor that continuously monitors and predicts store-to-load dependencies. The predictor provides feedback information about potential dependencies to the instruction execution pipeline, enabling dynamic decisions about whether to awaken dependent instructions. This feedback mechanism allows the system to adjust its behavior based on predicted dependency outcomes, reducing unnecessary replays while maintaining high throughput through speculative execution.

Inventive Principle:
Principle #23Feedback

3Productivity

If dependent instructions are awakened based on load instruction selection, then instruction-level parallelism is maximized, but unnecessary execution occurs when store data is invalid

Engineering Contradiction:
Improveinstruction-level parallelismVSAvoidexecution correctness
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by having the dependency predictor identify store-to-load dependencies before the load instruction executes and before dependent instructions are awakened. This advance prediction allows the system to determine whether it is safe to awaken dependent instructions based on the likelihood that the store data will be valid. By acting in advance, the system maximizes instruction-level parallelism while avoiding unnecessary execution when store data is likely to be invalid, thus maintaining execution correctness.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9606806B2Dependence-based replay suppression
Publication Date: 2017.03.28 ADVANCED MICRO DEVICES INC
  • US9606806B2 patent drawing
  • US9606806B2 patent drawing
  • US9606806B2 patent drawing

AI summary

A method includes selecting for execution in a processor a load instruction having at least one dependent instruction. Responsive to selecting the load instruction, the at least one dependent instruction is selectively awakened based on a status of a store instruction associated with the load instruction to indicate that the at least one dependent instruction is eligible for execution. A processor includes an instruction pipeline having an execution unit to execute instructions, a scheduler, and a controller. The scheduler selects for execution in the execution unit a load instruction having at least one dependent instruction. The controller, responsive to the scheduler selecting the load instruction, selectively awakens the at least one dependent instruction based on a status of a store instruction associated with the load instruction to indicate that the at least one dependent instruction is eligible for execution by the execution unit.