Depletion Mode FET ESD Protection Gate Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a demand for further reduction in on-resistance and drain capacitance per unit gate width in depletion type n-channel MOS field effect transistors to improve ESD protection in high-speed magnetic recording devices like HDDs, as existing techniques have limitations in achieving lower on-resistance while maintaining drain capacitance.
Innovation Solution
The field effect transistor design features a gate electrode formed along all sides of the drain region, with source and backgate regions arranged in a grid pattern to reduce on-resistance by a quarter while maintaining the same drain capacitance, achieved through the use of polysilicon gate electrodes and n-type source and drain regions, and the connection of backgate and source regions to apply a common potential.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate width is increased to reduce on-resistance, then the on-resistance decreases, but the drain capacitance per unit gate width remains high
Solution Approach 1:
The gate electrode is segmented into multiple sides (first gate side, second gate side, third gate side, fourth gate side) that surround the drain region from different directions. This segmentation allows the gate to control multiple channel regions independently, effectively increasing the total gate width and reducing on-resistance while maintaining compact layout and controlling drain capacitance.
Solution Approach 2:
The gate electrode extends in multiple spatial dimensions around the drain region, transitioning from a linear gate configuration to a multi-dimensional surrounding configuration. This dimensional change allows the gate to interface with channel regions from multiple directions, effectively increasing the gate width without proportionally increasing the area occupied by the drain capacitance.
2Reliability
If source regions are extended to reduce on-resistance, then the on-resistance decreases, but the channel width of the drain region is reduced
Solution Approach 1:
The source regions are positioned at specific locations (outside the gate sides) with optimized dimensions. The first and second source regions are located outside the first and second gate sides respectively, while the third and fourth source regions are positioned outside the third and fourth gate sides. This local optimization allows current to flow through multiple parallel paths without compromising the channel width under the gate, thereby reducing on-resistance while maintaining channel integrity.
Data Source
AI summary
A field effect transistor is provided having a reduced drain capacitance per unit gate width. A gate electrode 21 (G) having a plurality of sides is formed in first-conductivity first semiconductor region 14. Drain region 18D (D) is formed inside the gate electrode, and source regions 18S (S) are formed in respective regions outside the plurality of sides in widths that do not reduce the corresponding channel widths of the drain region. The gate electrode is formed along all the plurality of sides of the drain region in order to form a transistor.