Depletion FET Surface Channel for SOI Thickness Variations
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Solution Overview
Problem
Conventional semiconductor devices using silicon-on-insulator (SOI) substrates face undesirable variations in channel properties due to thickness variations, leading to inconsistent conduction characteristics and saturation current, limiting the scalability and performance of field effect transistor (FET) devices.
Innovation Solution
The use of surface channel regions in depletion field effect transistor devices, which are fabricated uniformly regardless of SOI thickness variations, along with the implementation of both back and top gates to enhance saturation current, allowing for smaller device sizes with comparable performance to larger conventional FET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional FET devices use SOI substrates with varying thickness, then manufacturing is simplified, but channel properties exhibit undesirable variations
Solution Approach 1:
The patent transitions from relying on vertical channel depth (affected by SOI thickness) to utilizing a lateral surface channel region. The channel is formed at the surface through selective oxidation and implantation processes, making it independent of the underlying SOI layer thickness. This dimensional shift from depth-dependent to surface-based channel formation resolves the contradiction between manufacturing simplicity and channel property consistency.
2Power
If conventional FET devices increase size to achieve higher saturation current, then current capability improves, but device area increases
Solution Approach 1:
The patent fundamentally changes the channel formation parameters by using selective oxidation to create a thin oxide layer followed by ion implantation to form the channel at the surface. This parameter change enables much higher saturation current density compared to conventional bulk channels, allowing smaller device areas to achieve the same current capability. The surface channel configuration with controlled oxidation and implantation doses achieves superior current characteristics without increasing device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in significantly increased saturation current, reducing variations in channel properties and enabling the fabrication of smaller devices with consistent performance, independent of SOI thickness, thereby overcoming the limitations of conventional FET devices.
Implementation Method 1
N-type channel stop regions and n-type surface channel regions are formed. A p-type channel stop resist mask is formed. P-type channel stop regions and p-type surface channel regions are then formed.
Data Source
AI summary
A high voltage field effect transistor device is fabricated. A substrate is provided. Isolation structures and well regions are formed therein. Drain well regions are formed within the well regions. An n-type channel stop resist mask is formed. N-type channel stop regions and n-type surface channel regions are formed. A p-type channel stop resist mask is formed. P-type channel stop regions and p-type surface channel regions are then formed. A dielectric layer is formed over the surface channel regions. Source regions are formed within the well regions. Drain regions are formed within the drain well regions. Back gate regions are formed within the well regions. Top gates are formed on the dielectric layer overlying the surface channel regions.