Depletion-Inducing Junctions for Parasitic Conduction in SOI ICs
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Solution Overview
Problem
Existing integrated circuit manufacturing techniques face challenges in effectively addressing parasitic surface conduction, particularly in high resistivity silicon on insulator wafers, which can lead to performance degradation and increased costs due to the need for complex designs and thermal instability.
Innovation Solution
The implementation of depletion-inducing junctions disposed in an array-like or checkerboard-like manner within the semiconductor substrate, which autonomously create depleted zones that interface with the electrically insulating layer, reducing parasitic surface conduction and enhancing compatibility with diverse manufacturing techniques while being resistant to thermal variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polysilicon layer is deposited and recrystallized to passivate the substrate surface, then parasitic surface conduction is suppressed, but the manufacturing process becomes complex and thermally unstable
Solution Approach 1:
The invention extracts the essential function of substrate passivation from the complex polysilicon deposition and recrystallization process. By using a simplified structure with the insulating layer directly contacting the semiconductor substrate and applying electrical bias to create depletion regions, the solution removes unnecessary manufacturing steps while maintaining the core functionality of suppressing parasitic surface conduction.
Solution Approach 2:
The invention changes the approach from material-based passivation (polysilicon layer) to field-based control (depletion regions created by electrical bias). By altering the physical state and mechanism of parasitic conduction suppression from chemical/material to electrical/field, the solution simplifies the manufacturing process while improving thermal stability.
2Stability of the object's composition
If rapid thermal annealing is performed at 950°C to recrystallize silicon, then polysilicon layer is formed, but thermal instability and process complexity increase
Solution Approach 1:
The invention performs preliminary formation of the insulating layer structure before any high-temperature processing. By establishing the depletion-inducing structure at lower temperatures and then applying electrical bias to create depletion regions, the solution avoids the need for subsequent 950°C rapid thermal annealing, thereby reducing thermal instability while achieving the desired functional layer formation.
3Reliability
If conventional guard-rings are formed in SOI layer, then isolation is achieved, but larger area is required and design flexibility is reduced
Solution Approach 1:
The invention moves the isolation mechanism from the lateral plane (conventional guard-rings extending in the SOI layer) to the vertical dimension (depletion regions extending from the insulating layer interface into the substrate). By creating depletion zones that extend downward from the interface, the solution achieves effective isolation with minimal lateral area, thereby improving space utilization and design flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively counters parasitic surface conduction, improves transistor performance, and reduces manufacturing costs by simplifying design and manufacturing processes, while maintaining compatibility with buried oxide layer technologies.
Implementation Method 1
a plurality of depletion-inducing junctions adapted to autonomously induce in the semiconductor substrate a plurality of depleted zones
Data Source
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AI summary
An integrated circuit device (100) comprises a semiconductor substrate (101) having a resistivity of at least 100 Ω.cm. An electrically insulating layer (102) contacts the semiconductor substrate (101). The electrically insulating layer (102) is susceptible of inducing in the semiconductor substrate (101) a parasitic surface conduction layer that interfaces with the electrically insulating layer (102). An electrical circuit (103) is located on the electrically insulating layer. The electrical circuit (103) comprises a section (105) capable of inducing an electrical field in the semiconductor substrate. The integrated circuit device (100) comprises a depletion-inducing junction (108, 109) of which at least a portion is comprised in the semiconductor substrate (101). The depletion-inducing junction (108, 109) can autonomously induce in the semiconductor substrate (101) a depleted zone that interfaces with a section of the electrically insulating layer (102) that lies in-between two sections (104, 105) of the electrical circuit (103).