Depletion Mode FeFET Low Voltage Programming
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Solution Overview
Problem
Current ferroelectric field-effect transistors (FeFETs) face challenges in precise voltage control, leading to difficulties in achieving both control and storage objectives in memory arrays due to the need for high-magnitude positive or negative voltages, which can cause unintended disturbances and data loss.
Innovation Solution
The development of a depletion-mode ferroelectric field-effect transistor (FeDFET) that operates with threshold voltages less than 0 volts, allowing for programming in both low-VT and high-VT states using minimal voltage, enabling precise control and storage without data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional enhancement-mode FeFETs are used with positive or negative high voltage pulses for programming, then the FeFET can be programmed into low-VT or high-VT states, but the high-magnitude voltages cause unintended disturbances and data loss in memory arrays
Solution Approach 1:
The patent changes the operating mode parameter from enhancement-mode to depletion-mode, which fundamentally alters the voltage requirements. Depletion-mode FeFETs can be programmed using low-magnitude positive or negative voltage pulses applied to the channel region, eliminating the need for high-magnitude gate voltage pulses that cause disturbances in memory arrays while maintaining reliable data retention
2Ease of manufacture
If high-magnitude voltage pulses are applied to program FeFETs, then programming can be achieved, but precise voltage control in channel regions becomes difficult
Solution Approach 1:
The patent changes the programming mechanism by applying voltage pulses directly to the channel region rather than through the gate electrode. This parameter change enables precise voltage control in the channel region using low-magnitude pulses, making it easier to achieve reliable programming without the complications of high-magnitude gate voltage control
Solution Approach 2:
The patent introduces an intermediate programming mechanism where voltage pulses are applied to the channel region through the substrate or body connection rather than directly through the gate. This intermediary approach allows for precise voltage control and programming without requiring high-magnitude gate voltages, resolving the control precision issue
3Productivity
If FeFETs are connected directly to major bit lines and word lines for programming, then memory array integration is achieved, but normal switchings in word lines and bit lines cause unintended disturbances
Solution Approach 1:
The patent changes the programming parameter from gate-voltage-based to channel-voltage-based operation. By applying low-magnitude voltage pulses directly to the channel region, the system can program FeFETs connected in memory arrays without causing unintended disturbances during normal word line and bit line switchings, maintaining both integration and data integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The FeDFET achieves reliable programming and storage with reduced voltage requirements, enhancing data retention and endurance in memory arrays by maintaining conductivity and non-conductivity states effectively, thus overcoming the limitations of conventional FeFETs.
Implementation Method 1
the ferroelectric layer has a first polarization state when the storage transistor is in the first programmed state and the ferroelectric layer has a second polarization state when the storage transistor is in the second programmed state
Data Source
AI summary
A depletion-mode FeFET (“FeDFET”) is programmable to a first programmed state, under a first set of voltage biasing conditions, and to a second programmed state, under a second set of voltage biasing conditions. In both the first and second programmed states, the storage transistor has a threshold voltage that is not greater than 0 volts. A memory circuit may be organized as memory cells, with each memory cell including select transistors, transistor switches and FeDFETs in a static random-access memory (SRAM) cell configuration.