Depletion Mode Circuit Protection for High Voltage Erase

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Solution Overview

Problem

High erase voltages in non-volatile microelectronic memory devices can damage low voltage circuits connected to bitlines during the erase operation, as these circuits are not designed to handle voltages above 6 volts.

Innovation Solution

A depletion mode circuit protection device is implemented, which includes a depletion region between high and low voltage contacts in the substrate, using n-dopant implantation to create a conductive gate that blocks high voltages from reaching low voltage circuitry by depleting and generating an electric field, preventing damage during erase operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If high voltage is applied to bitlines during erase operation, then erase operation can be performed, but low voltage circuits connected to bitlines are damaged

Engineering Contradiction:
Improveerase operation capabilityVSAvoidvoltage damage to low voltage circuits
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

A depletion mode circuit protection device is introduced as an intermediary component between the high voltage bitline and the low voltage circuitry. This device includes a depletion region formed by n-dopant implantation that acts as a voltage-blocking barrier, allowing the erase operation to proceed at high voltage while preventing the high voltage from reaching and damaging the low voltage circuits.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The circuit protection device utilizes parameter changes in the depletion region by controlling the n-dopant concentration and depletion depth to create a voltage-blocking characteristic. By adjusting these parameters, the device can block high voltages during erase operations while maintaining normal signal transmission during read/write operations, thus resolving the contradiction between erase capability and circuit protection.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If low voltage circuits are connected to bitlines, then circuit integration is achieved, but high voltage during erase operation damages the circuits

Engineering Contradiction:
Improvecircuit integrationVSAvoidcircuit protection during erase
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The depletion mode circuit protection device serves as a protective intermediary that enables low voltage circuits to be safely integrated with high voltage bitlines. It maintains the desired circuit integration while ensuring reliability by blocking damaging high voltages during erase operations, thus resolving the contradiction between integration and protection.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If no voltage blocking mechanism is used, then device complexity is low, but high voltage damages low voltage circuits

Engineering Contradiction:
Improvestructure simplicityVSAvoidvoltage damage
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The voltage blocking function is achieved through parameter changes in the semiconductor substrate by controlling n-dopant implantation depth and concentration. This creates a depletion region with specific electrical characteristics that blocks high voltage while maintaining a relatively simple device structure, thus resolving the contradiction between simplicity and protection capability.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The depletion mode circuit protection device effectively limits high voltages to below 6 volts, preventing damage to low voltage circuitry and ensuring safe operation during erase operations by behaving as a resistor and utilizing a depletion region to block excessive voltage.

Implementation Method 1

a depletion region between high and low voltage contacts in the substrate

Methodology Applied
Scientific EffectDepletion region:

Implementation Method 2

using n-dopant implantation to create a conductive gate that blocks high voltages from reaching low voltage circuitry by depleting and generating an electric field

Methodology Applied
Scientific EffectElectric field: Electric Field

Implementation Method 3

using n-dopant implantation to create a conductive gate

Methodology Applied
Scientific Effectn-dopant implantation: Ion Implantation

Data Source

PatentUS8243526B2Depletion mode circuit protection device
Publication Date: 2012.08.14 INTEL NDTM US LLC
  • US8243526B2 patent drawing
  • US8243526B2 patent drawing
  • US8243526B2 patent drawing

AI summary

A non-volatile microelectronic memory device that includes a depletion mode circuit protection device that prevents high voltages, which are applied to bitlines during an erase operation, from being applied to and damaging low voltage circuits which are electrically coupled to the bitlines.