Depletion-Mode Transistor Control Circuitry for GaN Safety
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Solution Overview
Problem
Depletion-mode transistors, such as GaN HEMTs, pose safety concerns due to their normally 'on' state, which can lead to cross-conduction issues during fault conditions, unlike enhancement-mode transistors that are inherently 'off' and prevent short circuits.
Innovation Solution
A circuitry configuration involving a depletion-mode transistor, an enhancement-mode NFET, a PFET, and fault detection circuitry, where the NFET and PFET control the depletion-mode transistor's state based on input logic and fault conditions, ensuring safe operation by turning off the depletion-mode transistor during faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a depletion-mode transistor is used, then switching performance is improved, but safety is worsened due to normally-on state causing cross-conduction during faults
Solution Approach 1:
The patent divides the control of the depletion-mode transistor into two independent parts: a first transistor controlling the source connection and a second transistor controlling the gate connection. This segmentation allows each transistor to be independently controlled, enabling the depletion-mode transistor to maintain its superior switching performance while preventing cross-conduction through coordinated control of the two transistors during fault conditions
Solution Approach 2:
The patent introduces intermediary transistors (first and second transistors) that act as mediators between the control circuit and the depletion-mode transistor. These intermediary transistors provide an additional layer of control that can isolate the depletion-mode transistor from harmful conditions, allowing it to operate at full performance during normal conditions while being protected during fault conditions
2Productivity
If a normally-on depletion-mode transistor is used, then switching performance is improved, but device complexity increases due to additional control circuitry needed
Solution Approach 1:
The patent merges the control functions for the source and gate of the depletion-mode transistor into a unified control structure where the first and second transistors are coordinated through shared control signals. This merging allows the additional control circuitry to be efficiently organized, reducing the overall complexity compared to separate independent control systems while maintaining the superior switching performance of the depletion-mode transistor
Data Source
Figure 1
AI summary
In described examples, a first transistor has: a drain coupled to a source of a depletion-mode transistor; a source coupled to a first voltage node; and a gate coupled to a control node. A second transistor has: a drain coupled to a gate of the depletion-mode transistor; a source coupled to the first voltage node; and a gate coupled through at least one first logic device to an input node. A third transistor has: a drain coupled to the gate of the depletion-mode transistor; a source coupled to a second voltage node; and a gate coupled through at least one second logic device to the input node.