Laterally Diffused Depletion Transistor for High-Voltage Leakage Control
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Solution Overview
Problem
Existing transistor designs, particularly enhancement mode transistors, face limitations in breakdown voltage, drain current management during overvoltage events, and performance in high-voltage applications, necessitating improved structural and fabrication techniques for better performance in integrated circuits.
Innovation Solution
The development of laterally diffused depletion mode transistors (LDMOS) that share a common drain with enhancement-mode transistors, utilizing unique junction designs and fabrication processes to enhance voltage handling capability and reduce leakage, without requiring additional masks or process steps, offering improved on-resistance and operational characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If enhancement mode transistors are used, then manufacturing simplicity is maintained, but breakdown voltage and voltage handling capability are limited
Solution Approach 1:
The patent merges enhancement mode and depletion mode transistors into a single integrated structure where they share a common drain region. This combination allows the circuit to benefit from both enhancement mode's manufacturing simplicity and depletion mode's high breakdown voltage characteristics, resolving the contradiction between reliability improvement and device complexity
Solution Approach 2:
The shared drain region serves multiple functions: it acts as the drain for both enhancement and depletion mode transistors, provides a common reference potential, and enables voltage handling capabilities beyond what a single transistor type could achieve. This multi-functionality improves breakdown voltage without proportionally increasing device complexity
2Reliability
If depletion mode transistors are implemented, then voltage handling capability is enhanced, but fabrication complexity increases
Solution Approach 1:
By combining enhancement and depletion mode transistors in a shared structure, the patent enables voltage handling enhancement while using a unified fabrication process that treats both transistor types similarly, reducing the overall fabrication complexity compared to implementing depletion mode transistors in isolation
Solution Approach 2:
The patent uses parameter changes in the doping profiles and junction depths to achieve depletion mode characteristics in specific regions while maintaining compatibility with standard CMOS fabrication processes. This allows voltage handling enhancement without requiring fundamentally different manufacturing approaches
3Reliability
If laterally diffused structures are used, then on-resistance is improved, but leakage current increases
Solution Approach 1:
The patent applies different doping concentrations and junction configurations in different local regions: lightly doped junctions in areas where leakage prevention is critical, and optimally doped regions where low on-resistance is prioritized. This local differentiation resolves the contradiction between improving on-resistance and reducing leakage current
Solution Approach 2:
The patent converts the potential harmful effect of laterally diffused structures (increased leakage) into a benefit by carefully controlling the diffusion profiles to create depletion regions that actually reduce leakage paths while maintaining the low on-resistance characteristics. The lateral diffusion that could increase leakage is instead used to create favorable electric field distributions
Data Source
AI summary
A transistor includes a first well region doped with second type dopants, a second well region doped with first type dopants, and a third well region. The transistor also includes a first isolation structure neighboring the first well region, a second isolation structure neighboring the the second well region and the third well region, a drain region doped with the first type dopants disposed in the third well region, a source region doped with the first type dopants disposed in the first well region, and a gate disposed at least partially over the second isolation structure. The transistor can be configured as a depletion mode transistor.