Depletion Mode Transistor Start-Up Circuit for AC-DC Converters
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Solution Overview
Problem
Existing AC-DC power converters face challenges in efficiently managing the start-up phase and transitioning to a steady-state phase, particularly in high voltage applications, where ensuring reliable power delivery and minimizing power consumption are critical.
Innovation Solution
A start-up circuit utilizing a depletion mode transistor to generate an initial voltage for controller enablement, followed by a maximum selector circuit that outputs the higher of two voltages to ensure a smooth handoff from the start-up phase to the steady-state phase, leveraging a transformer for energy transmission and feedback for power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional start-up circuit is used in high voltage AC-DC power converters, then the controller can be enabled during start-up phase, but the power consumption is high and the handoff to steady-state phase is not smooth
Solution Approach 1:
The patent changes the operational parameters of the transistor by using a depletion mode transistor instead of a conventional enhancement mode transistor. This parameter change in transistor type enables the circuit to operate with minimal power consumption during the start-up phase while maintaining reliable controller enablement, directly resolving the contradiction between reliability and power consumption.
2Reliability
If a conventional start-up circuit is used, then the controller is enabled, but the transition to steady-state phase lacks smooth handoff
Solution Approach 1:
The patent implements a dynamic handoff mechanism where the depletion mode transistor automatically transitions from being the primary power source during start-up to being bypassed when the steady-state voltage exceeds the start-up voltage. This dynamic operation provides smooth handoff between phases while maintaining simple circuit architecture, resolving the contradiction between reliability and device complexity.
3Use of energy by moving object
If minimal power consumption is achieved during start-up, then energy efficiency improves, but start-up reliability may be compromised
Solution Approach 1:
The depletion mode transistor inherently provides minimal off-state power consumption without requiring additional control circuitry or power management components. The transistor's natural characteristics enable it to serve dual purposes: maintaining reliability by enabling the controller while simultaneously achieving minimal power consumption, thus resolving the contradiction through self-service operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient power management, ensures reliable start-up and steady-state operations in high voltage applications, with minimal power consumption and effective handoff between start-up and steady-state phases, enhancing the overall performance of AC-DC power converters.
Implementation Method 1
A start-up circuit and method use a depletion mode transistor for generating a first voltage that enables a controller of the power converter in a start-up phase
Implementation Method 2
After the controller is enabled, the controller controls the output stage to output power which is used to generate a second voltage
Data Source
AI summary
A start-up circuit includes an input node, an output node, a reference node, and a depletion mode field-effect transistor (FET) having a first terminal coupled to the input node, a second terminal coupled to the output node, and a gate terminal. A Zener diode has a cathode coupled to the gate terminal of the FET and an anode coupled to the reference node. A first capacitor is coupled in parallel with the Zener diode, a first resistor is coupled between the gate terminal of the FET and the input node, and a second resistor is coupled between the second terminal of the FET and the reference node. The FET and the second resistor are configured to generate an output voltage on the output node, the output voltage being based on an input voltage on the input node and capped at a value below a peak value of the input voltage.