DEPOP Cyclic Selective Spacer Etch Nanowire Exposure
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Solution Overview
Problem
Conventional fabrication processes for multi-gate and nanowire transistors face challenges in scaling below the 10 nm node, leading to variability and limitations in further miniaturization, necessitating new methodologies to enhance performance and control in integrated circuit structures.
Innovation Solution
The implementation of a dry-etch-poly-open-polish (DEPOP) process using a cyclic selective spacer etch to fabricate nanowire-based integrated circuit structures, allowing for customizable control of nanowire exposure and connection, thereby tailoring the drive of individual transistors and improving stability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for multi-gate and nanowire transistors, then manufacturing simplicity and cost-effectiveness are maintained, but scaling below the 10 nm node becomes limited due to variability and process constraints
Solution Approach 1:
The fabrication process is divided into multiple sequential stages: forming sacrificial nanowires, depositing spacers, selectively removing spacers, and forming gate structures. This segmentation allows precise control at each step, enabling scaling below 10 nm while managing process variability through controlled intermediate states.
Solution Approach 2:
Sacrificial nanowires are formed first to define the precise location and dimensions of the final nanowire channel before the actual gate structure is created. This preliminary action establishes a template that ensures sub-10 nm precision in the final device geometry, overcoming direct patterning limitations.
2Productivity
If the number of nanowires in each transistor is fixed, then fabrication is simpler, but drive current and performance are limited
Solution Approach 1:
Different transistors are configured with different numbers of nanowires (one, two, three, or four) based on local performance requirements. The selective spacer removal process enables this local customization, allowing high-drive-current transistors to use more nanowires while simpler transistors use fewer, optimizing overall circuit performance.
Solution Approach 2:
The transistor configuration is made dynamic and adjustable rather than fixed. By controlling which spacers are removed and which nanowires are exposed, the effective number of active nanowires can be varied to match the drive current requirements of different circuit blocks, enabling performance optimization without increasing base fabrication complexity.
3Productivity
If all nanowires are exposed and connected, then drive current is maximized, but control over individual transistor performance is lost
Solution Approach 1:
Different regions of the substrate receive different treatments regarding spacer removal and nanowire exposure. This allows each transistor to be customized with the appropriate number of nanowires based on local circuit requirements, maintaining adaptability while enabling high drive current where needed through selective multi-nanowire configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of high-performance non-planar transistors with varying numbers of exposed nanowires, enhancing drive current and stability, suitable for future technology nodes, including logic and I/O applications.
Implementation Method 1
The spacer is removed from one or more of the vertically stacked nanowires on opposite sides of the gate using a cyclic selective spacer etch starting with the top nanowire
Data Source
AI summary
An integrated circuit structure comprises a semiconductor fin protruding through a trench isolation region above a substrate. A gate structure is over the semiconductor fin. A plurality of vertically stacked nanowires is through the gate structure, wherein the plurality of vertically stacked nanowires includes a top nanowire adjacent to a top of the gate structure, and a bottom nanowire adjacent to a top of the semiconductor fin. A dielectric material covers only a portion of the plurality of vertically stacked nanowires outside the gate structure, such that one or more one of the plurality of vertically stacked nanowires starting with the top nanowire is exposed from the dielectric material. Source and drain regions are on opposite sides of the gate structure connected to the exposed ones of the plurality of vertically stacked nanowires.