Depressed Wiring Layer for Semiconductor Module Thermal Stress
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Solution Overview
Problem
The challenge in semiconductor modules is the reliability of connection between electrodes and bumps due to thermal stress, which can lead to disconnection and peeling, especially as the size of semiconductor modules is miniaturized, and existing methods fail to adequately address the thermal expansion differences between materials.
Innovation Solution
A semiconductor module design featuring a substrate with an electrode, an insulating layer, and a wiring layer where the wiring layer is depressed toward the substrate, creating a moment that acts as an anchor for the bump, reducing thermal stress and improving connection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper is used for the metal plate and wiring pattern, then electrical conductivity is improved, but thermal stress is generated due to coefficient of thermal expansion difference with the insulating layer
Solution Approach 1:
The patent changes the physical state of the wiring layer from flat to depressed, creating a moment that generates a downward force component. This parameter change in the wiring layer's geometry allows it to counteract the upward peeling force caused by thermal stress, thereby improving connection reliability while maintaining the copper material's electrical conductivity
Solution Approach 2:
The patent converts the harmful thermal stress that causes peeling into a beneficial effect by creating a depressed wiring layer that generates a counteracting moment. The thermal expansion that previously caused damage now works together with the depressed structure to press the bump firmly against the electrode, transforming the harmful thermal stress into a stabilizing force
2Volume of moving object
If the semiconductor module is miniaturized by narrowing the gap between electrodes, then device size is reduced, but connection reliability deteriorates due to increased thermal stress concentration
Solution Approach 1:
The patent introduces a new geometric parameter - the depression depth of the wiring layer - which creates a moment arm that generates a downward force on the bump. This parameter change allows the structure to compensate for the reduced contact area in miniaturized devices, maintaining connection reliability even as device size decreases
Solution Approach 2:
The patent moves the wiring layer from a two-dimensional flat plane to a three-dimensional depressed structure. This dimensional change creates a moment that generates a vertical force component, adding a new degree of freedom to the stress distribution and improving bump-electrode connection in miniaturized modules
3Volume of moving object
If the bump area is reduced for further miniaturization, then device size is reduced, but the contact area between bump and electrode is reduced, making disconnection more likely
Solution Approach 1:
The patent changes the geometric parameter of the wiring layer from flat to depressed, creating a moment that generates a downward force on the bump. This parameter change compensates for the reduced bump contact area by applying an additional downward force that prevents peeling, thereby maintaining connection strength even in miniaturized bumps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the thermal reliability of the connection between the electrode and the bump by distributing thermal stress, reducing the likelihood of peeling and disconnection, and allows for cost-effective manufacturing without requiring additional apparatuses.
Implementation Method 1
as the second area of the wiring layer is thermally expanded, with the bump located in the first area as an anchor point, due to the heat generated while the semiconductor module is in operation, a moment having a component parallel with the surface of the substrate and a downward, vertical component is generated in the second area of the wiring layer
Data Source
AI summary
An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area. The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.