Derating Factor Selection for IC Yield and Speed
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Solution Overview
Problem
Wafer fabrication processes face yield loss due to conservative derating factors that lead to inefficient power utilization and slow ICs, with manufacturing variations and defects causing unusable wafers, especially at extreme fabrication conditions.
Innovation Solution
A test system and method using structural at-speed automated test equipment (ATE) to iterate tests at multiple clock frequencies, identifying performance deterioration in transistors with disparate electrical characteristics, allowing for the selection of a derating factor to optimize wafer fabrication processes by determining precise fabrication boundaries and adjusting derating factors accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conservative derating factors are applied to prevent yield loss, then manufacturing yield is improved, but IC speed performance deteriorates
Solution Approach 1:
The patent changes the parameter of derating factor from a fixed conservative value to a dynamically selected value based on measured transistor characteristics. By measuring actual transistor performance parameters (threshold voltage, drive current, leakage current) and selecting derating factors accordingly, the system optimizes the balance between yield and speed performance rather than applying uniform conservative derating across all devices.
2Productivity
If conservative derating factors are applied to ensure reliability, then manufacturing yield is improved, but power utilization efficiency deteriorates
Solution Approach 1:
The patent changes the power utilization efficiency by selecting derating factors based on actual measured transistor parameters rather than applying conservative default values. This allows the system to use transistors at or near their optimal power efficiency points while maintaining yield through statistical process control and measurement-based selection.
Solution Approach 2:
The patent implements feedback by measuring actual transistor characteristics (threshold voltage, drive current, leakage current) and using this measurement data to select appropriate derating factors. This closed-loop approach ensures that derating decisions are based on real device performance rather than conservative estimates, thereby improving power utilization efficiency while maintaining yield.
3Productivity
If strict fabrication targets are applied to manage yield conservatively, then manufacturing yield is improved, but design flexibility deteriorates
Solution Approach 1:
The patent changes from fixed strict fabrication targets to flexible, measurement-based derating factor selection. By measuring actual transistor parameters and selecting derating factors based on these measurements rather than predetermined strict targets, the system maintains yield while gaining design flexibility to optimize for different performance requirements.
Solution Approach 2:
The patent introduces dynamics by making derating factor selection adaptive rather than static. The system dynamically selects derating factors based on measured transistor characteristics, allowing the fabrication process to adapt to actual device variations rather than forcing all devices to meet rigid predetermined targets, thereby improving both yield and design flexibility.
Data Source
AI summary
A test system and method for selecting a derating factor to be applied to a ratio of transistors having disparate electrical characteristics in a wafer fabrication process. In one embodiment, the test system includes: (1) structural at-speed automated test equipment (ATE) operable to iterate structural at-speed tests at multiple clock frequencies over integrated circuit (IC) samples fabricated under different process conditions and (2) derating factor selection circuitry coupled to the structural at-speed ATE and configured to employ results of the structural at-speed tests to identify performance deterioration in the samples, the performance deterioration indicating the derating factor to be employed in a subsequent wafer fabrication process.