Descriptor Queue Parallel Data Processing

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Solution Overview

Problem

Conventional information processing apparatuses with multiple subprocessors face challenges in maintaining the order of input and output data due to varying processing times, requiring complex hardware arrangements or increased processing to manage data association, which can offset the benefits of parallel processing.

Innovation Solution

An information processing apparatus that employs a memory-based descriptor system, where stream processors acquire descriptors containing input and output address information to manage data association, allowing efficient parallel processing while minimizing management overhead and eliminating wasteful response times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple subprocessors are used for parallel processing, then processing capability is improved, but maintaining data order association becomes difficult

Engineering Contradiction:
Improveprocessing capabilityVSAvoiddata order association
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces a descriptor as an intermediary data structure that mediates between multiple subprocessors and the host processor. The descriptor contains input/output address information and status flags that enable reliable data association without requiring complex inter-subprocessor communication mechanisms.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements feedback mechanisms through status flags in the descriptor (such as completion flags) that allow the host processor to track the state of parallel processing operations. This feedback enables the system to maintain data order association by monitoring and coordinating subprocessor activities.

Inventive Principle:
Principle #23Feedback

2Reliability

If complex hardware arrangements are used to manage data association, then data order is maintained, but device complexity increases

Engineering Contradiction:
Improvedata order associationVSAvoidhardware arrangement
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the data association management function from complex hardware arrangements and consolidates it into a software-based descriptor structure. This extraction eliminates the need for additional complex hardware components while maintaining reliable data order association through structured data management.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If complex processing is used to manage data association, then data order is maintained, but processing time increases

Engineering Contradiction:
Improvedata order associationVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary actions by pre-allocating and pre-structuring descriptors before parallel processing begins. Input/output address information and control flags are prepared in advance, allowing subprocessors to efficiently manage data association without time-consuming runtime computations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7370123B2Information processing apparatus
Publication Date: 2008.05.06 RENESAS ELECTRONICS CORP
  • US7370123B2 patent drawing
  • US7370123B2 patent drawing
  • US7370123B2 patent drawing

AI summary

A descriptor queue composed of descriptors containing input address information that represents an address for storing data to be processed and output address information that represents an address for storing processed data is constructed and stored in a memory. A stream processor for performing a plurality of processes parallel to each other on the data to be processed acquires a descriptor from the memory, reads data to be processed from the memory according to the input address information contained in the descriptor, processes the data, and stores the processed data back into the memory according to the output address information contained in the descriptor.