Descriptor Ring Prefetching Circuitry for Memory Access Latency

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Solution Overview

Problem

Data processing systems with descriptor rings face delays due to the need for address translation, which requires a large number of processing cycles using mechanisms like page table walking.

Innovation Solution

Incorporating prefetching circuitry to detect pointers read from the descriptor ring and prefetch address translation data for corresponding memory addresses, reducing the delay associated with the first use of a pointer that requires address translation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If address translation is performed using page table walking mechanism, then address translation data can be obtained, but processing delay is introduced

Engineering Contradiction:
Improveaddress translation accuracyVSAvoidprocessing delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements a prefetching mechanism that anticipates future address translation needs by detecting pointers read from the descriptor ring and proactively fetching the corresponding address translation data before it is actually required. This preliminary action eliminates the processing delay that would otherwise occur when performing page table walking at the moment of need, while maintaining the reliability of address translation through validation against the page table structure.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If page table walking is performed to determine translation data, then accurate address translation is achieved, but system productivity decreases

Engineering Contradiction:
Improveaddress translation accuracyVSAvoidsystem efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The prefetching circuitry performs address translation data retrieval in advance by monitoring descriptor ring accesses and triggering page table walks before the actual memory access occurs. This allows the translation data to be ready in the translation lookaside buffer when needed, thereby maintaining translation accuracy while significantly improving system productivity by eliminating wait states during critical memory access paths.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a prefetching intermediary mechanism that sits between the descriptor ring and the memory access path. This intermediary detects pointer reads, initiates background page table walking operations, and ensures translation data is available before the actual memory access requires it, thus decoupling the translation overhead from the critical memory access path and improving overall system efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Use of energy by moving object

If address translation data is fetched on-demand, then memory bandwidth is conserved, but access speed decreases

Engineering Contradiction:
Improvememory bandwidth utilizationVSAvoidmemory access speed
Core Design Contradiction:
Use of energy by moving objectVSSpeed

Solution Approach 1:

The system performs address translation data fetching in advance by detecting pointers being read from the descriptor ring and proactively initiating page table walking operations. This prefetching approach loads translation data into the translation lookaside buffer before it is actually needed, thereby maintaining fast memory access speed while conserving memory bandwidth by only fetching data that is predicted to be needed soon rather than fetching all possible data.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9697136B2Descriptor ring management
Publication Date: 2017.07.04 ARM LTD
  • US9697136B2 patent drawing
  • US9697136B2 patent drawing
  • US9697136B2 patent drawing

AI summary

A data processing system utilizing a descriptor ring to facilitate communication between one or more general purpose processors and one or more devices employs a system memory management unit for managing access by the devices to a main memory. The system memory management unit uses address translation data for translating memory addresses generated by the devices into addresses supplied to the main memory. Prefetching circuitry within the system memory management unit serves to detect pointers read from the descriptor ring and to prefetch address translation data into the translation lookaside buffer of the system memory management unit.