Deserializer Clock Selection for Accurate Parallel Data Alignment
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Solution Overview
Problem
Deserializers face challenges in accurately converting serial data into parallel data due to difficulties in identifying the clock signal, leading to potential misalignment of parallel data output.
Innovation Solution
A deserializer design incorporating a shift register circuit, clock divider, clock selecting circuit, and data align circuit to utilize multiple clock signals with varying phases and frequencies to accurately align valid data, ensuring proper parallelization by detecting the clock signal edge at a specific time after the valid data period is identified.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a deserializer uses a single clock signal to convert serial data to parallel data, then the circuit structure is simple, but it is difficult to identify the clock signal and guarantee proper parallel data output
Solution Approach 1:
The patent divides the clock signal generation into multiple segmented clock signals (first clock signal, second clock signal, third clock signal) with different phases and frequencies. This segmentation allows the deserializer to identify valid data positions accurately by comparing multiple clock references, resolving the contradiction between simple circuit structure and reliable parallel data output.
Solution Approach 2:
The patent introduces a clock signal as an intermediary element that mediates between the serial input data and parallel output data. By using the clock signal to sample and synchronize data at specific phases, the system achieves accurate parallelization without requiring complex additional detection circuits.
2Measurement precision
If additional circuits are added to detect valid data positions, then parallel data alignment accuracy is improved, but device complexity increases
Solution Approach 1:
The patent employs a self-service mechanism where the clock signal itself carries the timing information needed for valid data detection. The multiple phases of the clock signal inherently indicate valid data positions, eliminating the need for separate detection circuits and maintaining simplicity while achieving high alignment accuracy.
Solution Approach 2:
The patent uses periodic clock signals with different phases to systematically scan through possible valid data positions. This periodic action allows the deserializer to identify the correct alignment point through rhythmic sampling, achieving precise data alignment without complex continuous detection circuits.
3Reliability
If multiple clock signals with different phases are used, then valid data identification is improved, but signal synchronization complexity increases
Solution Approach 1:
The patent performs preliminary action by pre-generating multiple clock signals with known phase relationships before the deserialization process. This advance preparation of clock references simplifies the synchronization task during actual operation, as the phase relationships are already established and can be directly applied to identify valid data positions.
Data Source
AI summary
A deserializer includes a shift register circuit that outputs N output data by shifting input data based on a first clock signal, a clock divider that outputs N second clock signals N-divided from the first clock signal and having N phases different from each other, and outputs one or more third clock signal divided to have a frequency less than that of the second clock signals, a clock selecting circuit that outputs a selected clock signal having an edge corresponding to a second time after N number of clock cycles of the first clock signal have elapsed from a first time at which a valid period is detected in a selection signal for selecting the input data based on the N second clock signals and the one or more third clock signals, and a data align circuit that parallelizes the N output data based on the selected clock signal.