Deserializer Data Alignment Under Inverted Internal Clock Phases
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Solution Overview
Problem
High-speed semiconductor systems require efficient data transmission schemes to handle high bandwidth data communication, but existing pre-fetch schemes struggle with aligning data correctly when internal clock signals have different phases, leading to errors in data alignment and transmission.
Innovation Solution
A deserializer is designed with a data aligner, selection signal generator, and selection output unit to align data using internal clock signals with different phases, generating higher and lower aligned data, and a phase detection signal to select the appropriate alignment based on the phase of the clock signals, ensuring accurate data output even when clock signals are inverted.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pre-fetch schemes are used to achieve high bandwidth data communication, then data transmission rate is improved, but data alignment accuracy deteriorates when internal clock signals have different phases
Solution Approach 1:
The system dynamically selects between different data alignment paths based on the phase relationship between first and second clock signals. The selection signal generator detects clock phase differences and controls the selection output unit to choose between first alignment data and second alignment data, enabling adaptive operation under varying clock conditions while maintaining both high transmission rate and alignment accuracy
Solution Approach 2:
The invention changes the alignment parameter selection based on clock phase conditions. When clock phases differ, the system switches between different alignment data sets (first alignment data versus second alignment data), effectively adapting the alignment parameter to match the actual clock phase relationship and prevent alignment errors
2Productivity
If multi-phase clock signals are used to latch and output data in parallel, then data transmission bandwidth is improved, but complexity of phase detection and selection increases
Solution Approach 1:
The selection signal generator acts as an intermediary that simplifies the complexity by centrally managing phase detection and selection logic. It receives clock signals, detects phase relationships, generates appropriate selection signals, and controls the selection output unit, thereby organizing the complex multi-phase operations into a coordinated sequence that achieves high bandwidth without excessive system complexity
Data Source
AI summary
Deserializers are provided. The deserializer includes a data aligner, a selection signal generator and a selection output unit. The data aligner is configured to align data in response to internal clock signals having different phases from each other to generate higher aligned data and lower aligned data. The selection signal generator is configured to detect a phase of one of the internal clock signals in response to a phase detection signal to generate a selection signal. The phase detection signal includes a pulse generated according to a write command signal and a write latency signal. The selection output unit is configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal.