Deserializer Sync Detection for Lost Bit Recovery
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Solution Overview
Problem
In high-speed serial communication systems, data bits can be lost due to a phase difference between the data packet and the recovery clock signal, leading to inaccurate data recovery.
Innovation Solution
A deserializer system comprising a first register, a sync detector, a lost bit storage unit, a second register, a packet combiner, and a third register, which loads and synchronizes data packets with a recovery clock signal, detects lost bits, and combines them to ensure accurate data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a deserializer recovers serial data using a recovery clock signal, then data communication speed is improved, but data bits may be lost due to phase difference between data packet and recovery clock
Solution Approach 1:
The patent applies preliminary action by detecting phase difference between the data packet and recovery clock signal before data recovery occurs. The sync detector identifies the phase offset in advance, allowing the system to pre-calculate compensation values and adjust sampling timing before actual data bits are recovered, preventing data loss proactively
Solution Approach 2:
The patent implements feedback by continuously monitoring the phase relationship between incoming data packets and the recovery clock signal. The sync detector provides real-time feedback about phase difference, which is used to dynamically adjust the sampling timing and compensate for phase drift, ensuring accurate data recovery despite speed variations
2Length of moving object
If transmission delay occurs in signal lines, then phase skew between data signal and recovery clock increases, but data bits are lost during parallel data recovery
Solution Approach 1:
The patent applies preliminary action by detecting phase skew caused by transmission delay before data recovery. The sync detector identifies the phase offset introduced by signal line transmission distance, allowing the system to pre-calculate compensation values and adjust sampling timing in advance, preventing data bit loss that would otherwise occur during parallel data recovery
Solution Approach 2:
The patent introduces an intermediary mechanism (sync detector and phase compensation logic) that mediates between the transmitted data signal and the recovery clock signal. This intermediary detects phase skew caused by transmission delay and applies corrective timing adjustments, acting as a buffer that prevents data bit loss despite variations in signal transmission distance
Data Source
AI summary
A deserializer including a plurality of registers, a sync detector, and a lost bit storage unit. If there is a phase difference between an external input data packet and a recovery clock signal transmitted together with the data packet, the sync detector generates an activated sync detect signal. The lost bit storage unit detects a data bit of the data packet corresponding to an activation point of the sync detect signal. The deserializer recovers the data packet by combining the detected data bit with the data packet.