Programmable Data Slip in High-Speed Deserializer Clocks
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Solution Overview
Problem
Existing high-speed deserialization systems are inflexible in slipping any number of bits and suffer from timing issues, requiring multiple control inputs and introducing opportunities for clock glitches, which can lead to synchronization loss and errors.
Innovation Solution
A high-speed deserializer with a programmable slip pulse generation circuit that generates deserialization clocks with robust timing, allowing for the selective slipping of one or more bits by delaying the sampling edges of the clocks, eliminating the need for multiple timing circuits and control signals, and maintaining synchronization among clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple control inputs and timing circuits are used to achieve bit slipping, then the flexibility to slip any number of bits is improved, but the device complexity increases and timing reliability deteriorates due to clock glitches
Solution Approach 1:
The patent combines multiple timing circuits and control inputs into a single timing circuit that generates all necessary slip pulses. Instead of using separate control inputs for each bit position, a single control input selectively enables the generation of slip pulses corresponding to different bit positions, thereby reducing device complexity while maintaining flexibility.
Solution Approach 2:
The timing circuit is designed to perform multiple functions: it generates slip pulses for different bit positions, maintains clock synchronization, and prevents clock glitches. This multi-functional approach eliminates the need for separate dedicated circuits for each function, reducing overall device complexity while preserving adaptability.
2Adaptability or versatility
If multiple timing circuits are used to control bit slipping, then the ability to slip specific bits is improved, but timing reliability deteriorates due to opportunities for clock glitches
Solution Approach 1:
By merging multiple timing circuits into a single unified timing circuit, the patent eliminates the interfaces and synchronization points between separate circuits where clock glitches could occur. The single timing circuit generates all slip pulses in a coordinated manner, ensuring timing reliability while maintaining the ability to slip specific bits through selective pulse generation.
3Measurement precision
If a programmable slip pulse is used to delay sampling edges, then the precision of bit selection is improved, but the device complexity increases due to programmable control
Solution Approach 1:
The patent achieves precise bit selection by changing the timing parameters of slip pulse generation rather than using complex programmable logic. A single control input selects which bit position corresponds to the active slip pulse by controlling the timing phase, thereby achieving precision through parameter control rather than structural complexity.
Data Source
AI summary
Provided are embodiments for operating a high-speed deserializer. Embodiments can include receiving a clock slip signal to enable operation of the slip pulse generation circuit, and generating a slip pulse signal using the slip pulse-controlled clock generation circuit, wherein the slip pulse signal is programmable to slip one or more bits of a serial input data. Embodiments can also include generating a plurality of deserialization clocks for sampling the serial input data using the slip pulse-controlled clock generation circuit, wherein the plurality of deserialization clocks are generated simultaneously with each other, and providing the plurality of deserialization clocks to the deserializer to selectively sample the serial input data.